Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

On 05/03/2016 07:30 PM, Shengzhou Liu wrote:

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com

drivers/ddr/fsl/ctrl_regs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)

Applied to fsl-qoriq master branch. Awaiting upstream. Thanks.

York