This patch adds the DDR4 init code. It is ported from the 2013 Cavium / Marvell U-Boot version with no functional change. This was done intentionally, as this code is very large and complex and is known to work on many boards "as-is". So any functional change might have introduced (hidden) incompatibilities.
Please note that the code has undergone many hours (read many days) of code cleanup and restructuring. Unfortunately its still not 100% checkpatch clean, as some warnings and checks can practically not be removed / addresses, like these here:
CHECK: Prefer kernel type 's8' over 'int8_t' -> 's8' can't be used on MIPS platforms, as its a register macro
or:
WARNING: Too many leading tabs - consider code refactoring + while (xor != 0) { -> I've restructured the code already and its very hard to remove all these "Too many leading tabs" warnings.
or other warnings / checks.
But compared to the original code in much better shape (checkpatch wise). I would have liked to include a checkpatch summary in this cover- letter, showing the "before" (original code) and "after" (this code) numbers, but unfortunately currently running checkpatch on the really big file (octeon3_lmc.c) leads to many false errors. I can only suspect that checkpatch has an issue handling this big file because of its size.
This code is tested on the Octeon3 EBB7304 EVK and works without any known issues with 1 or 2 DDR4 DIMM configurations (8 & 16 GiB).
Thanks, Stefan
Changes in v2: - Some unsupported Octeon families removed (only Octeon 2 & 3 supported in general) - Some unsupported Octeon families removed (only Octeon 2 & 3 supported in general) - Use readq/writeq in cvmx_read64_uint64/cvmx_write64_uint64 instead of readl/writel - Don't re-init after relocation - Some unsupported Octeon families removed (only Octeon 2 & 3 supported in general) - Only map 256MiB of RAM in U-Boot and print total size as well - Add year to copyright line
Aaron Williams (6): mips: octeon: Add octeon-model.h header mips: octeon Add cvmx/cvmx-lmcx-defs.h header mips: octeon: Add octeon_ddr.h header ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3) ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3) ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
Stefan Roese (3): mips: octeon: dts: mrvl,cn73xx.dtsi: Add memory controller DT node mips: octeon: dram.c: Add RAM driver support mips: octeon: octeon_ebb7304: Add DDR4 support
arch/mips/dts/mrvl,cn73xx.dtsi | 17 + arch/mips/mach-octeon/dram.c | 72 +- .../include/mach/cvmx/cvmx-lmcx-defs.h | 4576 ++++++ .../mach-octeon/include/mach/octeon-model.h | 317 + .../mach-octeon/include/mach/octeon_ddr.h | 988 ++ board/Marvell/octeon_ebb7304/board.c | 25 +- board/Marvell/octeon_ebb7304/board_ddr.h | 447 + configs/octeon_ebb7304_defconfig | 3 + drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/octeon/Kconfig | 17 + drivers/ram/octeon/Makefile | 8 + drivers/ram/octeon/dimm_spd_eeprom.c | 410 + drivers/ram/octeon/octeon3_lmc.c | 11484 ++++++++++++++++ drivers/ram/octeon/octeon_ddr.c | 2730 ++++ include/configs/octeon_common.h | 11 +- 16 files changed, 21093 insertions(+), 15 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h create mode 100644 arch/mips/mach-octeon/include/mach/octeon-model.h create mode 100644 arch/mips/mach-octeon/include/mach/octeon_ddr.h create mode 100644 board/Marvell/octeon_ebb7304/board_ddr.h create mode 100644 drivers/ram/octeon/Kconfig create mode 100644 drivers/ram/octeon/Makefile create mode 100644 drivers/ram/octeon/dimm_spd_eeprom.c create mode 100644 drivers/ram/octeon/octeon3_lmc.c create mode 100644 drivers/ram/octeon/octeon_ddr.c