On 11/09/2011 11:20 PM, Heiko Schocher wrote:
Hello Tom,
Tom Rini wrote:
This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value.
[snip]
+#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
You should use something like that here:
#define OMAP3_SDP_SDRC_xx_SHIFT 8 #define OMAP3_SDP_SDRC_yy (1 << 0)
#define SDP_3430_SDRC_RFR_CTRL_200MHz ((0x5e6 << OMAP3_SDP_SDRC_xx_SHIFT) | OMAP3_SDP_SDRC_yy)
OK, I hadn't forgotten about this, I've just been a bit busy. I broke out the TRM, split these values out into binary and, breaking it out into shifts won't help make it more understandable. It needs a better comment, which I will happily do. Bits 1:0 are autofresh enable is 0x1 and 0x2/0x3 are bursts. 7:2 are reserved (as are 24:31) and 8:23 are autorefresh counter value.