Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu111-revA.dts | 763 ++++++++++++++++++++++++++++ configs/xilinx_zynqmp_zcu111_revA_defconfig | 95 ++++ include/configs/xilinx_zynqmp_zcu111.h | 50 ++ 4 files changed, 909 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu111-revA.dts create mode 100644 configs/xilinx_zynqmp_zcu111_revA_defconfig create mode 100644 include/configs/xilinx_zynqmp_zcu111.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aa768935719d..77a0f8a30833 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -155,6 +155,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu104-revA.dtb \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ + zynqmp-zcu111-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1275-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts new file mode 100644 index 000000000000..1bb28de90b21 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -0,0 +1,763 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU111 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU111 RevA"; + compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_DOWN>; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + + tca6416_u22: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - MAX6643_OT_B + * 1 - MAX6643_FANFAIL_B + * 2 - MIO26_PMU_INPUT_LS + * 4 - SFP_SI5382_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMCP_HSPC_PRSNT_M2C_B + * 11 - CLK_SPI_MUX_SEL0 + * 12 - CLK_SPI_MUX_SEL1 + * 16 - IRPS5401_ALERT_B + * 17 - INA226_PMBUS_ALERT + * 3, 7, 13-15 - not connected + */ + }; + + i2c-mux@75 { /* u23 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + ina226@40 { /* u67 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u59 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u61 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u60 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u64 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u69 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + ina226@47 { /* u66 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@48 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + ina226@49 { /* u63 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u3 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u71 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + ina226@4c { /* u77 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + ina226@4d { /* u73 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + ina226@4e { /* u79 */ + compatible = "ti,ina226"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x44>; + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x45>; + }; + /* u68 IR38064 +0 */ + /* u70 IR38060 +1 */ + /* u74 IR38060 +2 */ + /* u75 IR38060 +6 */ + /* J19 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + + i2c-mux@74 { /* u26 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u88 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u46 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 { /* SI5328 - u48 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + sc18is603@2f { /* sc18is602 - u93 */ + compatible = "nxp,sc18is603"; + reg = <0x2f>; + /* 4 gpios for CS not handled by driver */ + /* + * USB2ANY cable or + * LMK04208 - u90 or + * LMX2594 - u102 or + * LMX2594 - u103 or + * LMX2594 - u104 + */ + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* FMC connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u27 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection FIXME */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + mux-wp { + groups = "sdio1_wp_0_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux { + function = "gpio0"; + groups = "gpio0_22_grp", "gpio0_23_grp"; + }; + + conf { + groups = "gpio0_22_grp", "gpio0_23_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp", "gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp", "gpio0_38_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-pull-up { + pins = "MIO22"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13", "MIO23", "MIO38"; + bias-disable; + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + no-1-8-v; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig new file mode 100644 index 000000000000..5c8842901e27 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu111" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU111" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_ISO_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/xilinx_zynqmp_zcu111.h b/include/configs/xilinx_zynqmp_zcu111.h new file mode 100644 index 000000000000..c488c2133c5a --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu111.h @@ -0,0 +1,50 @@ +/* + * Configuration for Xilinx ZynqMP zcu111 + * + * (C) Copyright 2017 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU111_H +#define __CONFIG_ZYNQMP_ZCU111_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 21 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU111_H */