Hi heiko,
On 2016年07月06日 17:34, Ziyuan Xu wrote:
From: Xu Ziyuan xzy.xu@rock-chips.com
So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init and phy_off for Synopsys phy on Rockchip platform.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com
Changes in v3:
- Make UOC_CON registers to be unfixed which should be got from DT
Changes in v2:
Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
Rework the behaviour in otg_phy_init() and otg_phy_off()
drivers/usb/phy/Makefile | 1 + drivers/usb/phy/rockchip_usb_syno_phy.c | 47 +++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 93d147e..8002a18 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -7,3 +7,4 @@
obj-$(CONFIG_TWL4030_USB) += twl4030.o obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o +obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c b/drivers/usb/phy/rockchip_usb_syno_phy.c new file mode 100644 index 0000000..ab049e1 --- /dev/null +++ b/drivers/usb/phy/rockchip_usb_syno_phy.c @@ -0,0 +1,47 @@ +/*
- Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h>
+#include "../gadget/dwc2_udc_otg_priv.h"
+#define UOC_CON(x) ((x) * 0x4)
As you know, dwc2 usb driver didn't apply devicetree model. It's hard to implement a compatible driver for Rockchip SoCs which use a same udc. For example, SOFT_CTRL bit is UOC_CON2[2] on RK3288 I can't assure it's also UOC_CON[2] on other socs. Do you have any good ideas?
+#define RESET_WRITE_ENA BIT(28) +#define PORT_RESET BIT(12) +#define PORT_NORMAL (0 << 12)
+#define SOFT_CTRL_WRITE_ENA BIT(18) +#define SOFT_CTRL_ENABLE BIT(2)
+#define SUSPEND_SETTING 0x2A +#define SUSPEND_WRITE_ENA (0x3f << 16)
+void otg_phy_init(struct dwc2_udc *dev) +{
- /* disable software control */
- writel(SOFT_CTRL_WRITE_ENA | (0 << 2),
dev->pdata->regs_phy + UOC_CON(2));- /* reset otg port */
- writel(RESET_WRITE_ENA | PORT_RESET,
dev->pdata->regs_phy + UOC_CON(0));- mdelay(1);
- writel(RESET_WRITE_ENA | PORT_NORMAL,
dev->pdata->regs_phy + UOC_CON(0));- udelay(1);
+}
+void otg_phy_off(struct dwc2_udc *dev) +{
- /* enable software control */
- writel(SOFT_CTRL_WRITE_ENA | SOFT_CTRL_ENABLE,
dev->pdata->regs_phy + UOC_CON(2));- /* enter suspend */
- writel(SUSPEND_WRITE_ENA | SUSPEND_SETTING,
dev->pdata->regs_phy + UOC_CON(3));+}