If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4.
This patch fixes the code accordingly.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- This patch supersedes http://patchwork.ozlabs.org/patch/177405/ . Changes for v2: - Consequences from the previous cleanup patches. - Add detailed description.
.../arch/arm/cpu/armv7/mx5/clock.c | 24 +++++++++++++++++++- .../arch/arm/include/asm/arch-mx5/crm_regs.h | 15 ++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-)
diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c index 137a6f9..6d984cb 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c @@ -216,6 +216,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) return ret; }
+#ifdef CONFIG_MX51 +/* + * This function returns the Frequency Pre-Multiplier clock. + */ +static u32 get_fpm(void) +{ + u32 mult; + u32 ccr = readl(&mxc_ccm->ccr); + + if (ccr & MXC_CCM_CCR_FPM_MULT) + mult = 1024; + else + mult = 512; + + return MXC_CLK32 * mult; +} +#endif + /* * Get mcu main rate */ @@ -321,7 +339,11 @@ static u32 get_lp_apm(void) u32 ccsr = readl(&mxc_ccm->ccsr);
if (ccsr & MXC_CCM_CCSR_LP_APM) - ret_val = MXC_CLK32 * 1024; +#if defined(CONFIG_MX51) + ret_val = get_fpm(); +#elif defined(CONFIG_MX53) + ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); +#endif else ret_val = MXC_HCLK;
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h index 56dceb4..ddfab70 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -82,6 +82,21 @@ struct mxc_ccm_reg { u32 cmeor; };
+/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (0x1 << 12) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) +#endif +#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_EN (0x1 << 8) +#endif +#define MXC_CCM_CCR_OSCNT_OFFSET 0 +#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) +#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) + /* Define the bits in register CCSR */ #if defined(CONFIG_MX51) #define MXC_CCM_CCSR_LP_APM (0x1 << 9)