Hi,
I'm experimenting to set up the initial stack in DCACHE instead of the internal SRAM on Ebony. In our SoC, no internal SRAM is available.
After reading README's <initial stack, global data> section and the sample code of ppc405 which sets the stack in DCACHE, I understand the ideas behind using DCACHE to be the initial stack. Well, I guess. 1. The CFG_INIT_RAM_ADDR is set to an address which nobody uses it. 2. Enable that area cacheable and all others are cache inhibited.
So I did several changes on cpu/ppc4xx/start.S, include/configs/EBONY.h, and board/ebony/init.S, trying to set up the stack correctly. 1. changed CFG_ISRAM_BASE to 0x40000000, whose original value is 0xc0000000. 2. commented out ISRAM setting in start.S 3. changed the TLB entries for ISRAM to the following.
#ifndef CFG_440_NO_ISRAM tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) #else tlbentry( CFG_ISRAM_BASE, SZ_256M, 0x40000000, 0, AC_R|AC_W|AC_X ) #endif
However these changes are not successful. A machine check exception occurs when setting up the stack (2nd stwu). What am I missing here?
/*----------------------------------------------------------------*/ /* Setup the stack in internal SRAM or DCACHE */ /*----------------------------------------------------------------*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l
li r0,0 stwu r0,-4(r1) stwu r0,-4(r1) /* Terminate call chain */
Thanks a lot, -Shawn.