Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit address bus width. In case more than 32 bit address is used, the new ext registers should be set.
Add support of ext registers.
Signed-off-by: Kumar Gala galak@kernel.crashing.org Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Based upon git://git.denx.de/u-boot.git (branch master)
arch/powerpc/include/asm/fsl_ifc.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index 7d95eb4..9aaa398 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -909,22 +909,24 @@ struct fsl_ifc_gpcm { */ struct fsl_ifc { u32 ifc_rev; - u32 res1[0x3]; + u32 res1[0x2]; struct { + u32 cspr_ext; u32 cspr; - u32 res2[0x2]; + u32 res2; } cspr_cs[FSL_IFC_BANK_COUNT]; - u32 res3[0x18]; + u32 res3[0x19]; struct { u32 amask; u32 res4[0x2]; } amask_cs[FSL_IFC_BANK_COUNT]; - u32 res5[0x18]; + u32 res5[0x17]; struct { + u32 csor_ext; u32 csor; - u32 res6[0x2]; + u32 res6; } csor_cs[FSL_IFC_BANK_COUNT]; - u32 res7[0x18]; + u32 res7[0x19]; struct { u32 ftim[4]; u32 res8[0x8];