Hi Stefano,
On Wed, Jan 29, 2014 at 10:47 AM, Stefano Babic sbabic@denx.de wrote:
Hi Dirk,
On 28/01/2014 17:53, Dirk Behme wrote:
Just for better understanding: Do you want to keep this intentionally simple? Or is there any special reason why you don't set additional (performance) registers here? E.g. the L2 PREFETCH and POWER registers, and the tag and data latency settings? Like done in the kernel.
This is a good point ! If it is true that L2 PREFETCH is turned on in mainline kernel, but it was *explicitely* turned off by Jason in FSL Kernel with the patch with subject ENGR00278489 (ARM PL310 errata: 7522719).
Mainline kernel and recent FSL kernels (3.0.35 4.1.0 or 3.10.17) keep L2 prefetch enabled.
Check this commit: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3....
Regards,
Fabio Estevam