On Sat, Jul 20, 2024 at 6:47 PM E Shattow lucent@gmail.com wrote:
Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree changes at runtime from board/starfive/visionfive2/spl.c
On Thu, Jul 18, 2024 at 6:38 PM Minda Chen minda.chen@starfivetech.com wrote:
Add Jh7110 Cadence USB dts node, Visionfive2 default setting is USB 2.0 device.
Signed-off-by: Minda Chen minda.chen@starfivetech.com
.../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/jh7110.dtsi | 52 +++++++++++++++++++ 2 files changed, 57 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e11babc1cd..44785bbee3 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -378,3 +378,8 @@ }; }; };
+&usb_cdns3 {
dr_mode = "peripheral";status = "okay";+}; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -371,6 +371,58 @@ status = "disabled"; };
usb0: usb@10100000 {compatible = "starfive,jh7110-usb";ranges = <0x0 0x0 0x10100000 0x100000>;#address-cells = <1>;#size-cells = <1>;starfive,stg-syscon = <&stg_syscon 0x4>;clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,<&stgcrg JH7110_STGCLK_USB_STB>,<&stgcrg JH7110_STGCLK_USB_APB>,<&stgcrg JH7110_STGCLK_USB_AXI>,<&stgcrg JH7110_STGCLK_USB_UTMI_APB>;clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,<&stgcrg JH7110_STGRST_USB_APB>,<&stgcrg JH7110_STGRST_USB_AXI>,<&stgcrg JH7110_STGRST_USB_UTMI_APB>;reset-names = "pwrup", "apb", "axi", "utmi_apb";usb_cdns3: usb@0 {compatible = "cdns,usb3";reg = <0x0 0x10000>,<0x10000 0x10000>,<0x20000 0x10000>;reg-names = "otg", "xhci", "dev";interrupts = <100>, <108>, <110>;interrupt-names = "host", "peripheral", "otg";phys = <&usbphy0>;phy-names = "cdns3,usb2-phy";};};usbphy0: phy@10200000 {compatible = "starfive,jh7110-usb-phy";reg = <0x0 0x10200000 0x0 0x10000>;clocks = <&syscrg JH7110_SYSCLK_USB_125M>,<&stgcrg JH7110_STGCLK_USB_APP_125>;clock-names = "125m", "app_125m";#phy-cells = <0>;};pciephy0: phy@10210000 {compatible = "starfive,jh7110-pcie-phy";reg = <0x0 0x10210000 0x0 0x10000>;#phy-cells = <0>;};pciephy1: phy@10220000 {compatible = "starfive,jh7110-pcie-phy";reg = <0x0 0x10220000 0x0 0x10000>;#phy-cells = <0>;};stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;-- 2.17.1
Access fault
starting USB... Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0 scanning bus usb@0 for devices... Unhandled exception: Load access fault EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL: 0000000000000004 EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc) resetting ...when I add only these:
int offset; offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */ fdt_add_subnode(fdt, offset, "usb0-0"); fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),"usb_pins", "/soc/pinctrl@13040000/usb0-0"); offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"); /* usb_pins */ fdt_create_phandle(fdt, offset); fdt_add_subnode(fdt, offset, "driver-vbus-pin"); offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin"); fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */ fdt_setprop_empty(fdt, offset, "bias-disable"); fdt_setprop_empty(fdt, offset, "input-disable"); fdt_setprop_empty(fdt, offset, "input-schmitt-disable"); fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */ fdt_setprop_string(fdt, offset, "pinctrl-names", "default"); fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"))); fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*&usb_cdns3 */ fdt_setprop_string(fdt, offset, "dr_mode", "host");
Success USB is working but PCI disabled if instead I add all of this:
int offset; offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */ fdt_add_subnode(fdt, offset, "usb0-0"); fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),"usb_pins", "/soc/pinctrl@13040000/usb0-0"); offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"); /* usb_pins */ fdt_create_phandle(fdt, offset); fdt_add_subnode(fdt, offset, "driver-vbus-pin"); offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin"); fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */ fdt_setprop_empty(fdt, offset, "bias-disable"); fdt_setprop_empty(fdt, offset, "input-disable"); fdt_setprop_empty(fdt, offset, "input-schmitt-disable"); fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */ fdt_setprop_string(fdt, offset, "status", "disabled"); offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */ fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */ fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /* append <magic number> */ fdt_setprop_u32(fdt, offset, "starfive,stg-syscon", fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148); /* append <magic number> */ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4); /* append <magic number> */ fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */ fdt_setprop_string(fdt, offset, "pinctrl-names", "default"); fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"))); fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*&usb_cdns3 */ fdt_setprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000"))); /* = <&usbphy0> */ fdt_appendprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10210000"))); /* append <&pciephy0> */ fdt_setprop(fdt, offset, "phy-names", "cdns3,usb2-phy\0cdns3,usb3-phy", sizeof("cdns3,usb2-phy\0cdns3,usb3-phy")); fdt_setprop_string(fdt, offset, "dr_mode", "host");
I have made some mistake for devicetree and USB2.0 with keeping pcie0 (not disable)? or is there a problem with the implementation?
Best regards, -E Shattow
P.S. here is with debug logging:
drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop: assigned-clock-rates: <not found> drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for phy@10200000 drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for phy@10200000 drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result for phy@10200000: phy@10200000 (ret=0) drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result for phy@10200000: phy@10200000 (ret=0) drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop: assigned-clock-rates: <not found> drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for clock-controller@13020000 drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for clock-controller@13020000 drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result for clock-controller@13020000: clock-controller@13020000 (ret=0) drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result for clock-controller@13020000: clock-controller@13020000 (ret=0) drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for clock-controller@10230000 drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for clock-controller@10230000 drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result for clock-controller@10230000: clock-controller@10230000 (ret=0) drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result for clock-controller@10230000: clock-controller@10230000 (ret=0) common/event.c:113- notify_dynamic() Sending event 5/(unknown) to spy 'efi_disk add' drivers/usb/cdns3/drd.c:287- cdns3_drd_init() cdns-usb3-host usb@0: DRD version v1 (ID: 0004024e, rev: 00000200) drivers/usb/cdns3/drd.c:297- cdns3_drd_init() cdns-usb3-host usb@0: Controller strapped to HOST drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop: dr_mode: host drivers/phy/starfive/phy-jh7110-usb2.c:58- usb2_phy_set_mode() jh7110_usb2_phy phy@10200000: Changing phy to 1 drivers/usb/cdns3/core.c:304-cdns3_hw_role_switch() cdns-usb3-host usb@0: Switching role 0 -> 1cdns-usb3-host usb@0: Waiting till Host mode is turned on drivers/usb/cdns3/core.c:309-cdns3_hw_role_switch() cdns-usb3-host usb@0: set 1 has failed, back to 0 drivers/usb/cdns3/core.c:375- cdns3_probe() cdns-usb3-host usb@0: Cadence USB3 core: probe succeed common/event.c:113- notify_dynamic() Sending event 5/(unknown) to spy 'efi_disk add' drivers/core/ofnode.c:394-ofnode_read_u32_index() ofnode_read_u32_index: companion: (not found) scanning bus usb@0 for devices... Unhandled exception: Load access fault EPC: 00000000fff7f50e RA: 00000000fff7f508 TVAL: 0000000000000004 EPC: 000000004024d50e RA: 000000004024d508 reloc adjusted
Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
resetting ...
-E