From: Ye Li ye.li@nxp.com
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/clock.h | 3 ++ arch/arm/mach-imx/imx9/clock.c | 41 ++++++++++++++++++++++++++ 2 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index fcf04d66f05..d96f126a1d1 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index); int enable_i2c_clk(unsigned char enable, u32 i2c_num); u32 imx_get_i2cclk(u32 i2c_num); u32 mxc_get_clock(enum mxc_clock clk); +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void);
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 55cbb40f328..5d2bc0d2f8f 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable) } }
+#ifdef CONFIG_SPL_BUILD +void dram_pll_init(ulong pll_val) +{ + configure_fracpll(DRAM_PLL_CLK, pll_val); +} + +void dram_enable_bypass(ulong clk_val) +{ + switch (clk_val) { + case MHZ(400): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); + break; + case MHZ(333): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3); + break; + case MHZ(200): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4); + break; + case MHZ(100): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8); + break; + default: + printf("No matched freq table %lu\n", clk_val); + return; + } + + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from PLL to CCM */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM); +} + +void dram_disable_bypass(void) +{ + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from CCM to PLL */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); +} +#endif + int clock_init(void) { int i;