Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an ARCH specific macro is introduced to implement SoC specific errata workaround implementations.
Signed-off-by: Nishanth Menon nm@ti.com --- README | 5 +++++ arch/arm/cpu/armv7/start.S | 14 ++++++++++++++ 2 files changed, 19 insertions(+)
diff --git a/README b/README index a28ff133ee05..2e53e0c5757d 100644 --- a/README +++ b/README @@ -621,6 +621,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
+ NOTE: The following are machine specific errata that are enabled + with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an + SoC specific implementation of the erratum workaround to + function. + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10aee6..3b814d8f42d3 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -163,6 +163,20 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + mrc p15, 0, r0, c0, c0, 0 @ r0 has Read Main ID Register (MIDR) + mov r1, r0, lsr #20 @ get variant field + and r1, r1, #0xf @ r1 has CPU variant + and r2, r0, #0xf @ r2 has CPU revision + mov r3, r1, lsl #4 @ shift variant field for combined value + orr r3, r2, r3 @ r3 has combined CPU variant + revision + /* C Prototype: + * void arch_cp15_errata_workaround(u32 midr, u32 variant, + * u32 rev, u32 comb); + */ + b arch_cp15_errata_workaround @ Do Machine specific errata WAs +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)