On Tue, Jun 11, 2013 at 10:34:22AM -0500, Andrew Gabbasov wrote:
After waiting for the command completion event, the interrupt status bits, that occured to be set by that time, are cleared by writing them back. It is supposed, that it should be command related bits (command complete and may be command errors).
However, in some cases the DMA already completes by that time before the full transaction completes. The corresponding DINT bit gets set and then cleared before even entering the loop, waiting for data part completion. That waiting loop never gets this bit set, causing the operation to hang. This is reported to happen, for example, for write operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II 8GB card.
The solution could be to explicitly clear only command related interrupt status bits. However, since subsequent processing does not rely on any command bits state, it could be easier just to remove clearing of any bits at that point, leaving them all until all data processing completes. After that the whole register will be cleared at once.
Also, on occasion, interrupts masking moved to before writing the command, just for the case there should be no chance of interrupt between the first command and interrupts masking.
Reported-by: Dirk Behme dirk.behme@de.bosch.com Signed-off-by: Andrew Gabbasov andrew_gabbasov@mentor.com Acked-by: Dirk Behme dirk.behme@de.bosch.com
Applied, Thanks!
Andy