Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.
arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/e500mc_power_isa.dtsi | 33 ++++++++++++++++++ arch/powerpc/dts/p2041.dtsi | 63 ++++++++++++++++++++++++++++++++++ arch/powerpc/dts/p2041rdb.dts | 18 ++++++++++ board/freescale/p2041rdb/README | 18 ++++++++++ configs/P2041RDB_NAND_defconfig | 3 ++ configs/P2041RDB_SDCARD_defconfig | 3 ++ configs/P2041RDB_SPIFLASH_defconfig | 3 ++ configs/P2041RDB_defconfig | 3 ++ 9 files changed, 145 insertions(+) create mode 100644 arch/powerpc/dts/e500mc_power_isa.dtsi create mode 100644 arch/powerpc/dts/p2041.dtsi create mode 100644 arch/powerpc/dts/p2041rdb.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index bee1e2d..3123249 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb +dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/e500mc_power_isa.dtsi b/arch/powerpc/dts/e500mc_power_isa.dtsi new file mode 100644 index 0000000..e486ae5 --- /dev/null +++ b/arch/powerpc/dts/e500mc_power_isa.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e500mc Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi new file mode 100644 index 0000000..9aa0422 --- /dev/null +++ b/arch/powerpc/dts/p2041.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P2041"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts new file mode 100644 index 0000000..6e9d9c0 --- /dev/null +++ b/arch/powerpc/dts/p2041rdb.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041RDB Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p2041.dtsi" + +/ { + model = "fsl,P2041RDB"; + compatible = "fsl,P2041RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 9b5539f..79f77e4 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -85,6 +85,24 @@ Boot from SPI flash SW1[1-5] = 10100 Note: 1 stands for 'on', 0 stands for 'off'
+Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p2041rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin' +instead of u-boot.bin for all boot. + CPLD command ============ The CPLD is used to control the power sequence and some serdes lane diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 44966d8..73baf49 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 3d558c5..d75f8b1 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 4fb3794..925f0cd 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 2a70296..1923b7a 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y