add aristainetso board version CSL.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/dts/Makefile | 2 + .../imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 ++++ .../imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 ++ .../imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ++++++ arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/aristainetos.c | 4 +- board/aristainetos/common/Kconfig | 1 + configs/aristainetos2bcsl_defconfig | 115 ++++++++ include/configs/aristainetos2.h | 21 ++ 14 files changed, 595 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi create mode 100644 configs/aristainetos2bcsl_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1cd120a98e..e7ae3e40f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -578,6 +578,8 @@ dtb-y += \ imx6dl-aristainetos2_7.dtb \ imx6dl-aristainetos2b_4.dtb \ imx6dl-aristainetos2b_7.dtb \ + imx6dl-aristainetos2b_csl_4.dtb \ + imx6dl-aristainetos2b_csl_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi new file mode 100644 index 0000000000..654ac122a1 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts new file mode 100644 index 0000000000..bfbb799f20 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b csl board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi new file mode 100644 index 0000000000..70d195ecbf --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts new file mode 100644 index 0000000000..ecf767da6c --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi new file mode 100644 index 0000000000..8c2ed70075 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi new file mode 100644 index 0000000000..fa4dadefb6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b-csl board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_blue_2 { + label = "led_blue2"; + gpios = <&expander 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_green_2 { + label = "led_green2"; + gpios = <&expander 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_red_2 { + label = "led_red2"; + gpios = <&expander 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_yellow_2 { + label = "led_yellow2"; + gpios = <&expander 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + wlan_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* WLAN Module Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index b3819d816d..7787dbaf6d 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -147,6 +147,17 @@ config TARGET_ARISTAINETOS2B imply CMD_SATA imply CMD_DM
+config TARGET_ARISTAINETOS2BCSL + bool "Support aristainetos2-revB CSL" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2e1d84d412..9eb3c3b9d8 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -21,3 +21,15 @@ config SYS_BOARD_VERSION default 3
endif + +if TARGET_ARISTAINETOS2BCSL + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 4 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 4fa0ad2e98..9685c032ab 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -5,6 +5,7 @@ F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig +F: configs/aristainetos2bcsl_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -20,3 +21,9 @@ F: arch/arm/dts/imx6dl-aristainetos2b_7.dts F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index ca6155947b..88090799a6 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -490,7 +490,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) +#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ + (CONFIG_SYS_BOARD_VERSION == 3) || \ + (CONFIG_SYS_BOARD_VERSION == 4)) , { .bus = -1, .addr = 0, diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index a15993e2de..6f1c825d80 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -4,6 +4,7 @@ config SYS_BOARD_VERSION version of aristainetos board version 2 version 2 3 version 2b + 4 version 2bcsl
config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig new file mode 100644 index 0000000000..d83d52fbc6 --- /dev/null +++ b/configs/aristainetos2bcsl_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2BCSL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" +CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index d2646d26da..64a819df13 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -107,6 +107,27 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#elif (CONFIG_SYS_BOARD_VERSION == 4) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on;led led_red2 on;\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" #else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \