2013.02.02. 20:35 keltezéssel, Daniel Schwierzeck írta:
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c index 9ba711d..9333242 100644 --- a/board/qemu-malta/qemu-malta.c +++ b/board/qemu-malta/qemu-malta.c @@ -8,6 +8,9 @@
#include <common.h>
+#include <asm/io.h> +#include <asm/malta.h>
phys_size_t initdram(int board_type) { return CONFIG_SYS_MEM_SIZE; @@ -18,3 +21,11 @@ int checkboard(void) puts("Board: MIPS Malta CoreLV (Qemu)\n"); return 0; }
+void _machine_restart(void) +{
void __iomem *reset_base;reset_base = (void __iomem *) CKSEG1ADDR(MALTA_RESET_BASE);__raw_writel(le32_to_cpu(GORESET), reset_base);don't you need to swap from CPU endianess to register/bus endinaness? I think regisers/bus are always BE and only CPU changes between LE/BE. So we either need __raw_writel(cpu_to_be32(v),a) or writel_be32(v,a).
The register uses the same endianness as the CPU, so we have to write either a LE or BE value depending on the CPU endianness.
This means that we should use the __raw_writel accessor with a plain GORESET value. That method works in Linux but does not work in U-Boot.
The Malta board needs the CONFIG_SWAP_IO_SPACE for PCI device acccess. If this config options is set then the __raw_writel accessor will swap the given value on BE systems. So I have to pre-swap the value with le32_to_cpu to make it working correctly.
The relevant definitions from 'arch/mips/include/asm/io.h':
#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
#define __ioswab8(x) (x) #define __ioswab16(x) swab16(x) #define __ioswab32(x) swab32(x)
#else ... #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel
Maybe here is the time to fix these accessors in asm/io.h?
-Gabor