Re: [U-Boot] [PATCH v3 7/8] arm: socfpga: fix SPL booting from fpga OnChip RAM

On 08/13/2018 03:32 PM, Simon Goldschmidt wrote:

Marek Vasut <marex@denx.de mailto:marex@denx.de> schrieb am Mo., 13. Aug. 2018, 15:29:

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> To boot from fpga OnChip RAM, some changes are required in SPL
> to ensure the code is linked to the correct address (in contrast
> to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> copying it to SRAM) and that fpga OnChip RAM stays accessible while
> SPL runs (don't disable fpga bridges).
>
> This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> for socfpga gen5 boards.
>
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com
<mailto:simon.k.r.goldschmidt@gmail.com>>

I wonder if you can somehow detect that you're booting from FPGA , using
BSEL readout maybe, but then I guess you have a problem with the link
address ... hrm.

I was trying that, but we need to fix the linker address anyway, so...

Right

> ---
>
> Changes in v3: this patch is new in v3
> Changes in v2: None
>
>  arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
>  arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
>  arch/arm/mach-socfpga/spl_gen5.c  |  3 ++-
>  include/configs/socfpga_common.h  |  5 +++++
>  4 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig
b/arch/arm/mach-socfpga/Kconfig
> index 5c1df2cf1f..a909395aac 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
>       default "socfpga_vining_fpga" if
TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> 
>  endif
> +
> +if TARGET_SOCFPGA_GEN5
> +
> +config SPL_SOCFPGA_BOOT_FROM_FPGA
> +     bool "Allow booting SPL from FPGA OnChip RAM"

If you converted SPL_TEXT_BASE to Kconfig , then selecting this could
flip it to correct value. Can you do that ?

Sure, I'll try that.

Look at tools/moveconfig.py

> +     default n
> +     help
> +       Boot from FPGA: this changes the linker address for SPL
code to run
> +       from FPGA OnChip memory instead of SRAM and ensures FPGA
OnChip RAM
> +       stays accessible while SPL runs.
> +
> +endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
> index 32af1a9084..00df16d0b1 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -177,7 +177,8 @@ static void socfpga_nic301_slave_ns(void)
> 
>  void socfpga_init_bus_mapping(void)
>  {
> -     socfpga_bridges_reset(1);
> +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +             socfpga_bridges_reset(1);
> 
>       socfpga_nic301_slave_ns();
> 
> @@ -189,7 +190,13 @@ void socfpga_init_bus_mapping(void)
>       setbits_le32(&scu_regs->sacr, 0xfff);
> 
>       /* Configure the L2 controller to make SDRAM start at 0 */
> -     writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
> +     if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> +             /* remap.mpuzero, keep fpga bridge enabled */
> +             writel(0x9, &nic301_regs->remap);
> +     } else {
> +             /* remap.mpuzero */
> +             writel(0x1, &nic301_regs->remap);
> +     }
>       writel(0x1, &pl310->pl310_addr_filter_start);
>  }
> 
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c
b/arch/arm/mach-socfpga/spl_gen5.c
> index 631905fbee..1a16c46915 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -161,5 +161,6 @@ void board_init_f(ulong dummy)
>               hang();
>       }
> 
> -     socfpga_bridges_reset(1);
> +     if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +             socfpga_bridges_reset(1);
>  }
> diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
> index 2fb207c86a..3cdde0f926 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   * 0xFFEz_zzzz ...... Malloc area (grows up to top)
>   * 0xFFE3_FFFF ...... End of SRAM (top)
>   */
> +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> +/* SPL executed from FPGA */
> +#define CONFIG_SPL_TEXT_BASE         0xC0000000
> +#else
>  #define CONFIG_SPL_TEXT_BASE         CONFIG_SYS_INIT_RAM_ADDR
> +#endif
>  #define CONFIG_SPL_MAX_SIZE          CONFIG_SYS_INIT_RAM_SIZE
> 
>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>


-- 
Best regards,
Marek Vasut