Hi Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 02 May 2020 18:03 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot Mailing List u-boot@lists.denx.de; Atish Patra atish.patra@wdc.com; Palmer Dabbelt palmerdabbelt@google.com; Paul Walmsley paul.walmsley@sifive.com; Jagan Teki jagan@amarulasolutions.com; Troy Benjegerdes troy.benjegerdes@sifive.com; Anup Patel anup.patel@wdc.com; Sagar Kadam sagar.kadam@sifive.com; Rick Chen rick@andestech.com; Lukas Auer lukas.auer@aisec.fraunhofer.de; Simon Glass sjg@chromium.org Subject: Re: [PATCH v7 13/22] riscv: cpu: fu540: Add support for cpu fu540
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Hi Pragnesh,
On Sat, May 2, 2020 at 6:08 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com
arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 ++++++++++++++ arch/riscv/cpu/fu540/Makefile | 7 +++++++ arch/riscv/cpu/fu540/cpu.c | 22 ++++++++++++++++++++ arch/riscv/cpu/fu540/dram.c | 38
+++++++++++++++++++++++++++++++++++
5 files changed, 83 insertions(+) create mode 100644 arch/riscv/cpu/fu540/Kconfig create mode 100644 arch/riscv/cpu/fu540/Makefile create mode 100644 arch/riscv/cpu/fu540/cpu.c create mode 100644 arch/riscv/cpu/fu540/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fb5fe5afff..3044609971 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -57,6 +57,7 @@ source "board/sifive/fu540/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/fu540/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig new file mode 100644 index 0000000000..b2cb155d6d --- /dev/null +++ b/arch/riscv/cpu/fu540/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
+config GENERIC_RISCV
This should be SIFIVE_FU540
Will update in v8, thanks for the review.
boolselect ARCH_EARLY_INIT_Rimply CPUimply CPU_RISCVimply RISCV_TIMERimply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)imply CMD_CPUimply SPL_CPU_SUPPORTimply SPL_OPENSBIimply SPL_LOAD_FITdiff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile new file mode 100644 index 0000000000..44700d998c --- /dev/null +++ b/arch/riscv/cpu/fu540/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 SiFive, Inc +# Pragnesh Patel pragnesh.patel@sifive.com
+obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/fu540/cpu.c b/arch/riscv/cpu/fu540/cpu.c new file mode 100644 index 0000000000..13a69ef0cc --- /dev/null +++ b/arch/riscv/cpu/fu540/cpu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com */
+#include <common.h> +#include <irq_func.h>
+/*
- cleanup_before_linux() is called just before we call linux
- it prepares the processor for linux
- we disable interrupt and caches.
- */
+int cleanup_before_linux(void) +{
disable_interrupts();cache_flush();return 0;+} diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c new file mode 100644 index 0000000000..1dc77efeca --- /dev/null +++ b/arch/riscv/cpu/fu540/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com */
+#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <linux/sizes.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
return fdtdec_setup_mem_size_base(); }+int dram_init_banksize(void) +{
return fdtdec_setup_memory_banksize(); }+ulong board_get_usable_ram_top(ulong total_size) { #ifdef +CONFIG_64BIT
/** Ensure that we run from first 4GB so that all* addresses used by U-Boot are 32bit addresses.** This in-turn ensures that 32bit DMA capable* devices work fine because DMA mapping APIs will* provide 32bit DMA addresses only.*/if (gd->ram_top > SZ_4G)return SZ_4G;+#endif
return gd->ram_top;+}
Other than that, Reviewed-by: Bin Meng bmeng.cn@gmail.com
Regards, Bin