Index: u-boot/CREDITS =================================================================== RCS file: /cvsroot/u-boot/u-boot/CREDITS,v retrieving revision 1.31 diff -u -r1.31 CREDITS --- u-boot/CREDITS 25 Mar 2004 14:59:07 -0000 1.31 +++ u-boot/CREDITS 2 Apr 2004 14:29:56 -0000 @@ -83,6 +83,10 @@ E: damm@opensource.se D: 8xxrom +N: George G. Davis +E: gdavis@mvista.com +D: Board ports for ADS GraphicsClient+ and Intel Assabet + N: Arun Dharankar E: ADharankar@ATTBI.Com D: threads / scheduler example code Index: u-boot/MAKEALL =================================================================== RCS file: /cvsroot/u-boot/u-boot/MAKEALL,v retrieving revision 1.61 diff -u -r1.61 MAKEALL --- u-boot/MAKEALL 25 Mar 2004 19:29:38 -0000 1.61 +++ u-boot/MAKEALL 2 Apr 2004 14:29:56 -0000 @@ -123,7 +123,7 @@ ## StrongARM Systems ######################################################################### -LIST_SA="dnp1110 gcplus lart shannon" +LIST_SA="assabet dnp1110 gcplus lart shannon" ######################################################################### ## ARM7 Systems Index: u-boot/MAINTAINERS =================================================================== RCS file: /cvsroot/u-boot/u-boot/MAINTAINERS,v retrieving revision 1.36 diff -u -r1.36 MAINTAINERS --- u-boot/MAINTAINERS 25 Mar 2004 19:29:38 -0000 1.36 +++ u-boot/MAINTAINERS 2 Apr 2004 14:29:56 -0000 @@ -299,6 +299,11 @@ # Board CPU # ######################################################################### +George G. Davis + + assabet SA1100 + gcplus SA1100 + Thomas Elste modnet50 ARM720T (NET+50) Index: u-boot/Makefile =================================================================== RCS file: /cvsroot/u-boot/u-boot/Makefile,v retrieving revision 1.103 diff -u -r1.103 Makefile --- u-boot/Makefile 25 Mar 2004 19:29:38 -0000 1.103 +++ u-boot/Makefile 2 Apr 2004 14:29:58 -0000 @@ -936,6 +936,9 @@ ## StrongARM Systems ######################################################################### +assabet_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 assabet + dnp1110_config : unconfig @./mkconfig $(@:_config=) arm sa1100 dnp1110 --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/board/assabet/assabet.c 2004-04-01 23:46:56.000000000 -0500 @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* + * Board dependent initialisation + */ + +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 +#define SMC_IO_SHIFT 2 +#define NCR_0 (*((volatile u_char *)(0x100000a0))) +#define NCR_ENET_OSC_EN (1<<3) + +static inline u8 +readb(volatile u8 * p) +{ + return *p; +} + +static inline void +writeb(u8 v, volatile u8 * p) +{ + *p = v; +} + +static void +smc_init(void) +{ + u8 ecor; + u8 ecsr; + volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); + + NCR_0 |= NCR_ENET_OSC_EN; + udelay(100); + + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; + ecsr |= ECSR_IOIS8; + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + udelay(100); +} + +static void +neponset_init(void) +{ + smc_init(); +} + +int +board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = 25; /* Intel Assabet Board */ + gd->bd->bi_boot_params = 0xc0000100; + + neponset_init(); + + return 0; +} + +int +dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} Binary files /dev/null and u-boot/board/assabet/assabet.o differ --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/board/assabet/config.mk 2004-04-01 23:02:01.000000000 -0500 @@ -0,0 +1,7 @@ +# +# SA-1110 based Intel Assabet board +# +# The Intel Assabet 1 bank of 32 MiB SDRAM +# + +TEXT_BASE = 0xc1f00000 Binary files /dev/null and u-boot/board/assabet/libassabet.a differ --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/board/assabet/Makefile 2004-04-01 22:07:06.000000000 -0500 @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# 2004 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := assabet.o +SOBJS := setup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Binary files /dev/null and u-boot/board/assabet/setup.o differ --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/board/assabet/setup.S 2004-04-01 23:08:18.000000000 -0500 @@ -0,0 +1,136 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define ASSABET_BCR (0x12000000) +#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) +#define ASSABET_SCR_nNEPONSET (1 << 9) +#define NEPONSET_LEDS (0x10000010) + + +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ + + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +mdcnfg: .long 0x72547254 +mdcas00: .long 0xaaaaaa7f +mdcas01: .long 0xaaaaaaaa +mdcas02: .long 0xaaaaaaaa +msc0: .long 0x4b384370 +msc1: .long 0x22212419 +mecr: .long 0x994a994a +mdrefr: .long 0x04340327 +mdcas20: .long 0xaaaaaa7f +mdcas21: .long 0xaaaaaaaa +mdcas22: .long 0xaaaaaaaa +msc2: .long 0x42196669 +smcnfg: .long 0x00000000 + +BCR: .long ASSABET_BCR +BCR_DB1110: .long ASSABET_BCR_DB1110 +LEDS: .long NEPONSET_LEDS + + + .globl memsetup +memsetup: + + /* Setting up the memory and stuff */ + + ldr r0, MEM_BASE + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + ldr r1, mdrefr + str r1, [r0, #MDREFR] + ldr r1, mecr + str r1, [r0, #MECR] + ldr r1, msc0 + str r1, [r0, #MSC0] + ldr r1, msc1 + str r1, [r0, #MSC1] + ldr r1, msc2 + str r1, [r0, #MSC2] + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Load something to activate bank */ + ldr r2, MEM_START +.rept 8 + ldr r3, [r2] +.endr + + /* Enable SDRAM */ + orr r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + ldr r1, BCR + ldr r2, BCR_DB1110 + str r2, [r1] + + ldr r1, LEDS + mov r0, #0x3 + str r0, [r1] + + /* All done... */ + mov pc, lr --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/board/assabet/u-boot.lds 2004-04-01 23:08:38.000000000 -0500 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} --- /dev/null 2003-01-30 05:24:37.000000000 -0500 +++ u-boot/include/configs/assabet.h 2004-04-02 09:45:11.000000000 -0500 @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * Configuation settings for the Intel Assabet board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +#define CONFIG_INIT_CRITICAL + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ +#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ + +#undef CONFIG_USE_IRQ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ +#define CONFIG_LAN91C96_BASE 0x18000000 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" +#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" +#define CFG_AUTOLOAD "n" /* No autoload */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ + +#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ + +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMSTART +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_SIZE +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +#undef CFG_FLASH_PROTECTION +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_ENV_IS_IN_FLASH 1 + +#if defined(CFG_ENV_IS_IN_FLASH) +#define CFG_ENV_IN_OWN_SECTOR 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#endif + +#endif /* __CONFIG_H */