On Wed, Jul 11, 2018 at 12:52:07PM +0530, Jagan Teki wrote:
On Wed, Jul 11, 2018 at 12:44 PM, Maxime Ripard maxime.ripard@bootlin.com wrote:
On Wed, Jul 11, 2018 at 12:37:04PM +0530, Jagan Teki wrote:
On Wed, Jul 11, 2018 at 12:23 PM, Vasily Khoruzhick anarsoul@gmail.com wrote:
On Mon, Jul 9, 2018 at 12:17 PM, Jagan Teki jagan@amarulasolutions.com wrote:
Only H3 and H5 have 4 PHYS so restrict rst_mask only for them.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 3096f12c1c..81fcd1f910 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -117,7 +117,7 @@ struct sun4i_usb_phy_info { .gpio_vbus = CONFIG_USB3_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, -#ifdef CONFIG_MACH_SUN6I +#ifdef CONFIG_MACH_SUNXI_H3_H5
It should be handled by compatibles, not ifdefs. Phy driver is proper DM driver, so you can use .data in device ids array.
True, but since it' already have ifdef and more over this code will drop very soon, we are planning to support CLK and RST[1] (max of v2018.11).
Says who?
Me with USB clocks and resets.
I'd really prefer to have something when it's ready, rather than trying to push to meet a deadline that we enforced on ourselves, and end up with a tons of bugs to fix. The latest PHY patches should be a pretty good example on why we *shouldn't* do that.
These series fixes not certainly related to sunxi because of recent changes, were there in musb shutdown code and PHY changes were there before with legacy.
Well, all the fallout with EHCI being broken surely wasn't there before. It took us a year or so to have support for all the SoCs we support in Linux and have a somewhat robust, complete clock support. Thinking that it can be done and merged within 3 monthes is unreasonable.
Maxime