Attached a patch that adds support for the 16-bit wide bus of System ACE CF besides the existing support for the 8-bit wide bus.
The patch also sets the FORCECFGMODE bit in the control register when the System ACE CF configuration controller is reset before reading a sector. Without this bit set System ACE CF reconfigures an FPGA if the CFGMODE pin is active whenever a sector is read.
The third hunk fixes a typo.
- Peter
--- u-boot.orig/common/cmd_ace.c 2005-09-22 23:53:00.000000000 -0700 +++ u-boot/common/cmd_ace.c 2005-09-26 07:40:41.000000000 -0700 @@ -22,8 +22,9 @@ /* * The Xilinx SystemACE chip support is activated by defining * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE - * to set the base address of the device. This code currently - * assumes that the chip is connected via a byte-wide bus. + * to set the base address of the device. CFG_SYSTEMACE_WIDTH + * selects the bus width the chip is connected with. Valid + * settings are 8 or 16. * * The CONFIG_SYSTEMACE also adds to fat support the device class * "ace" that allows the user to execute "fatls ace 0" and the @@ -137,6 +138,11 @@ block_dev_desc_t * systemace_get_dev(in systemace_dev.removable = 1; systemace_dev.block_read = systemace_read;
+ if(CFG_SYSTEMACE_WIDTH == 8) + ace_writew(0, 0); + else + ace_writew(1, 0); + init_part(&systemace_dev);
} @@ -227,7 +233,7 @@ static unsigned long systemace_read(int
/* Reset the configruation controller */ val = ace_readw(0x18); - val|=0x0080; + val|=0x0088; ace_writew(val, 0x18);
retry = trans * 16; @@ -249,7 +255,7 @@ static unsigned long systemace_read(int retry -= 1; }
- /* Clear the configruation controller reset */ + /* Clear the configuration controller reset */ val = ace_readw(0x18); val&=~0x0080; ace_writew(val, 0x18);
* Add System ACE CF support for 16-bit bus width Add fix to ignore CFGMODE pin when resetting the System ACE CF configuration controller to avoid reconfiguration of FPGAs when reading sectors. Patch by Peter Ryser, 26 Sep 2005