In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
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Changes in v4: None Changes in v3: - only initialize mcounteren CSR for S-mode - only touch satp in M-mode U-Boot - move the implementation to arch_cpu_init_dm()
Changes in v2: - use csr_set() to set MSTATUS_FS - only enabling the cycle, time, and instret counters - change to use satp
arch/riscv/cpu/cpu.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index a2ebaf3..fa7d869 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -8,6 +8,7 @@ #include <dm.h> #include <log.h> #include <asm/csr.h> +#include <asm/encoding.h> #include <dm/uclass-internal.h>
/* @@ -57,7 +58,31 @@ static int riscv_cpu_probe(void)
int arch_cpu_init_dm(void) { - return riscv_cpu_probe(); + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + /* Enable FPU */ + if (supports_extension('d') || supports_extension('f')) { + csr_set(MODE_PREFIX(status), MSTATUS_FS); + csr_write(fcsr, 0); + } + + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + /* + * Enable perf counters for cycle, time, + * and instret counters only + */ + csr_write(mcounteren, GENMASK(2, 0)); + + /* Disable paging */ + if (supports_extension('s')) + csr_write(satp, 0); + } + + return 0; }
int arch_early_init_r(void)