On 12 December 2014 at 18:35, Bin Meng bmeng.cn@gmail.com wrote:
The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support.
Is this necessary to enable flash at BIOS media?
How about other flash media's, is this specific to x86 cpu to store u-boot always in spi flash.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v3:
- Add a commit message for the SPI support
Changes in v2:
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()
arch/x86/cpu/queensbay/tnc.c | 26 +++++++++++++++++++++++++- arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++ include/configs/crownbay.h | 2 ++ 3 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 8b9815f..8637cdc 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -6,18 +6,42 @@
#include <common.h> #include <asm/io.h> +#include <asm/pci.h> #include <asm/post.h> +#include <asm/arch/tnc.h> #include <asm/arch/fsp/fsp_support.h> #include <asm/processor.h>
+static void unprotect_spi_flash(void) +{
u32 bc;bc = pci_read_config32(PCH_LPC_DEV, 0xd8);bc |= 0x1; /* unprotect the flash */pci_write_config32(PCH_LPC_DEV, 0xd8, bc);+}
int arch_cpu_init(void) {
struct pci_controller *hose;int ret;post_code(POST_CPU_INIT);#ifdef CONFIG_SYS_X86_TSC_TIMER timer_set_base(rdtsc()); #endif
return x86_cpu_init_f();
ret = x86_cpu_init_f();if (ret)return ret;ret = pci_early_init_hose(&hose);if (ret)return ret;unprotect_spi_flash();return 0;}
int print_cpuinfo(void) diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h new file mode 100644 index 0000000..67c5e05 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -0,0 +1,15 @@ +/*
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _X86_ARCH_TNC_H_ +#define _X86_ARCH_TNC_H_
+#include <pci.h>
+/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+#endif /* _X86_ARCH_TNC_H_ */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 2314e62..a051b11 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -45,6 +45,8 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
+#define CONFIG_SPI_FLASH_SST
/* Video is not supported */ #undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
1.8.2.1
thanks!