Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/ccu.h | 47 ++++++++++++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sunxi/Kconfig | 18 ++++++++ drivers/clk/sunxi/Makefile | 9 ++++ drivers/clk/sunxi/clk_a64.c | 62 +++++++++++++++++++++++++++ drivers/clk/sunxi/clk_sunxi.c | 58 +++++++++++++++++++++++++ 7 files changed, 196 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h create mode 100644 drivers/clk/sunxi/Kconfig create mode 100644 drivers/clk/sunxi/Makefile create mode 100644 drivers/clk/sunxi/clk_a64.c create mode 100644 drivers/clk/sunxi/clk_sunxi.c
diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h new file mode 100644 index 0000000000..f628c893de --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/ccu.h @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#ifndef _ASM_ARCH_CCU_H +#define _ASM_ARCH_CCU_H + +/** + * ccu_clk_map - common clock unit clock map + * + * @off: ccu clock offset + * @bit: ccu clock bit value + * @ccu_clk_set_rate: ccu clock set rate func + */ +struct ccu_clk_map { + u16 off; + u32 bit; + int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate); +}; + +/** + * struct ccu_desc - common clock unit descriptor + * + * @clks: mapping clocks descriptor + * @num_clks: number of mapped clocks + */ +struct ccu_desc { + struct ccu_clk_map *clks; + unsigned long num_clks; +}; + +/** + * struct sunxi_clk_priv - sunxi clock private structure + * + * @base: base address + * @desc: ccu descriptor + */ +struct sunxi_clk_priv { + void *base; + const struct ccu_desc *desc; +}; + +extern struct clk_ops sunxi_clk_ops; + +#endif /* _ASM_ARCH_CCU_H */ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a99abed9e9..b4992e9ff1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -88,6 +88,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sunxi/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 146283c723..7cefcd99a0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig new file mode 100644 index 0000000000..bf5ecb3801 --- /dev/null +++ b/drivers/clk/sunxi/Kconfig @@ -0,0 +1,18 @@ +config CLK_SUNXI + bool "Clock support for Allwinner SoCs" + depends on CLK && ARCH_SUNXI + default y + help + This enables support for common clock driver API on Allwinner + SoCs. + +if CLK_SUNXI + +config CLK_SUN50I_A64 + bool "Clock driver for Allwinner A64" + default MACH_SUN50I + help + This enables common clock driver support for platforms based + on Allwinner A64 SoC. + +endif # CLK_SUNXI diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile new file mode 100644 index 0000000000..fb20d28333 --- /dev/null +++ b/drivers/clk/sunxi/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2018 Amarula Solutions. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o + +obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c new file mode 100644 index 0000000000..9393a01ccf --- /dev/null +++ b/drivers/clk/sunxi/clk_a64.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun50i-a64-ccu.h> + +static struct ccu_clk_map a64_clks[] = { + [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, + [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, + [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, + [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, + [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL }, + + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, + [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, + [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, + [CLK_USB_HSIC_12M] = { 0x0cc, BIT(11), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(16), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL }, +}; + +static const struct ccu_desc sun50i_a64_ccu_desc = { + .clks = a64_clks, + .num_clks = ARRAY_SIZE(a64_clks), +}; + +static int a64_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static const struct udevice_id a64_clk_ids[] = { + { .compatible = "allwinner,sun50i-a64-ccu", + .data = (ulong)&sun50i_a64_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun50i_a64) = { + .name = "sun50i_a64_ccu", + .id = UCLASS_CLK, + .of_match = a64_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a64_clk_probe, +}; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c new file mode 100644 index 0000000000..791b1ac7f2 --- /dev/null +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ccu.h> +#include <linux/log2.h> + +static int sunxi_clk_enable(struct clk *clk) +{ + struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); + struct ccu_clk_map *map = &priv->desc->clks[clk->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + clk->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg | map->bit, priv->base + map->off); + + return 0; +} + +static int sunxi_clk_disable(struct clk *clk) +{ + struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); + struct ccu_clk_map *map = &priv->desc->clks[clk->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + clk->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg & ~map->bit, priv->base + map->off); + + return 0; +} + +struct clk_ops sunxi_clk_ops = { + .enable = sunxi_clk_enable, + .disable = sunxi_clk_disable, +};