Hi!
I tested this and it works fine. I also happen to have the glue layer ported from the Linux somewhere on my machine. If you're interested, please reach out to me and I'll arrange a patch. I have a few remarks on this patch:
On 3/27/24 9:07 AM, wefu@redhat.com wrote:
From: Wei Fu wefu@redhat.com
Signed-off-by: Wei Fu wefu@redhat.com Co-authored-by: Yixun Lan dlan@gentoo.org
arch/riscv/Kconfig | 1 + arch/riscv/cpu/c9xx/Kconfig | 12 ++++++++ arch/riscv/cpu/c9xx/Makefile | 5 ++++ arch/riscv/cpu/c9xx/cpu.c | 51 ++++++++++++++++++++++++++++++++ arch/riscv/cpu/c9xx/dram.c | 36 ++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 2 ++ board/thead/th1520_lpi4a/Kconfig | 3 +- 7 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ac52c5e6da..ac3b802abe 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -97,6 +97,7 @@ source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" +source "arch/riscv/cpu/c9xx/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/c9xx/Kconfig b/arch/riscv/cpu/c9xx/Kconfig new file mode 100644 index 0000000000..5a84bcacd6 --- /dev/null +++ b/arch/riscv/cpu/c9xx/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017-2020 Alibaba Group Holding Limited
+config RISCV_THEAD
- bool
- select ARCH_EARLY_INIT_R
- imply CPU
- imply CPU_RISCV
- imply RISCV_TIMER
- imply RISCV_RDTIME
- imply CMD_CPU
diff --git a/arch/riscv/cpu/c9xx/Makefile b/arch/riscv/cpu/c9xx/Makefile new file mode 100644 index 0000000000..e3f776cb41 --- /dev/null +++ b/arch/riscv/cpu/c9xx/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017-2020 Alibaba Group Holding Limited
+obj-y += cpu.o dram.o diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c new file mode 100644 index 0000000000..4b21edd62b --- /dev/null +++ b/arch/riscv/cpu/c9xx/cpu.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2017-2020 Alibaba Group Holding Limited
- */
+#include <asm/cache.h> +#include <asm/csr.h> +#include <cpu_func.h>
+/*
- cleanup_before_linux() is called just before we call linux
- it prepares the processor for linux
- we disable interrupt and caches.
- */
+int cleanup_before_linux(void) +{
- cache_flush();
- return 0;
+}
+void flush_dcache_range(unsigned long start, unsigned long end) +{
- register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
Isn't this just round_down/ALIGN_DOWN macro?
- for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
asm volatile(".long 0x0295000b"); /* dcache.cpa a0 */- sync_is();
+}
+void invalidate_dcache_range(unsigned long start, unsigned long end) +{
- register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
asm volatile(".long 0x02b5000b"); /* dcache.cipa a0 */
`th.dcache.cipa` not only invalidates the dcache, but also flushes it which is not expected here. In practice, this leads to a bug with the dwmac driver: when U-Boot handles an ARP request, it overwrites the ARP request with the ARP response in-place, directly in the ring buffer[^1]. When re-using the same buffer later on, the driver will flush this data instead of invalidating it[^2], and you'll read the ARP response you just sent instead of the packet just written by the chip.
This can easily be reproduced by downloading a big file using TFTP. As soon as you receive an ARP request, U-Boot hangs, timeouts and requests the packet again. It also makes TCP completely unusable.
You can use `th.dcache.ipa` instead, as implemented in `invalid_dcache_range`.
[^1] https://github.com/u-boot/u-boot/blob/a5ec56aea1a56737a4e124d058a6920d16f5e6... [^2] https://github.com/u-boot/u-boot/blob/a5ec56aea1a56737a4e124d058a6920d16f5e6...
- sync_is();
+}
+void invalid_dcache_range(unsigned long start, unsigned long end)
I think this isn't used anywhere.
+{
- register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
asm volatile(".long 0x02a5000b"); /* dcache.ipa a0 */- sync_is();
+} diff --git a/arch/riscv/cpu/c9xx/dram.c b/arch/riscv/cpu/c9xx/dram.c new file mode 100644 index 0000000000..614d7bf1cc --- /dev/null +++ b/arch/riscv/cpu/c9xx/dram.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
- */
+#include <fdtdec.h> +#include <init.h> +#include <linux/sizes.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- return fdtdec_setup_mem_size_base();
+}
+int dram_init_banksize(void) +{
- return fdtdec_setup_memory_banksize();
+}
+phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{
- /*
* Ensure that we run from first 4GB so that all* addresses used by U-Boot are 32bit addresses.** This in-turn ensures that 32bit DMA capable* devices work fine because DMA mapping APIs will* provide 32bit DMA addresses only.*/- if (gd->ram_top >= SZ_4G)
return SZ_4G - 1;- return gd->ram_top;
+} diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 986f951c31..3102de6cbb 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -145,6 +145,8 @@ #define CSR_MARCHID 0xf12 #define CSR_MHARTID 0xf14
+#define sync_is() asm volatile (".long 0x01b0000b")
I believe this instruction is also T-Head specific (at least my disassembler doesn't know it). I doubt it belongs here.
Best regards, Nils
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \ diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig index 622246127c..bef0638e80 100644 --- a/board/thead/th1520_lpi4a/Kconfig +++ b/board/thead/th1520_lpi4a/Kconfig @@ -11,7 +11,7 @@ config SYS_VENDOR default "thead"
config SYS_CPU
- default "generic"
default "c9xx"
config SYS_CONFIG_NAME default "th1520_lpi4a"
@@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_EARLY_INIT_R
- select RISCV_THEAD imply CPU imply CPU_RISCV imply RISCV_TIMER if RISCV_SMODE