On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
i.MX8MM/MN/MP/MQ - added support for JR driver model. sec is initialized based on job ring information processed from device tree.
Signed-off-by: Gaurav Jain gaurav.jain@nxp.com
Reviewed-by: Ye Li ye.li@nxp.com
Best regards, Ye Li
arch/arm/Kconfig | 2 +- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + arch/arm/mach-imx/imx8m/Kconfig | 23 ++++++++++++++++++++++ arch/arm/mach-imx/imx8m/soc.c | 10 +++++++++- board/freescale/imx8mm_evk/spl.c | 9 ++++++++- board/freescale/imx8mn_evk/spl.c | 8 ++++++-- board/freescale/imx8mp_evk/spl.c | 13 ++++++++++-- board/freescale/imx8mq_evk/spl.c | 9 +++++++-- drivers/crypto/fsl/jr.c | 14 ++++++++++--- scripts/config_whitelist.txt | 1 + 10 files changed, 78 insertions(+), 12 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d59562665..af7aad3f9e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -794,7 +794,7 @@ config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select GPIO_EXTRA_HEADER
- select SYS_FSL_HAS_SEC if IMX_HAB
- select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE select DM diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1..ff8de53f67 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -72,6 +72,7 @@ #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach- imx/imx8m/Kconfig index ccaf106be5..3fbdd5c233 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -38,6 +38,11 @@ config TARGET_IMX8MQ_EVK bool "imx8mq_evk" select IMX8MQ select IMX8M_LPDDR4
- select FSL_CAAM
- select FSL_BLOB
- select MISC
- select ARCH_MISC_INIT
- select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" @@ -50,6 +55,11 @@ config TARGET_IMX8MM_EVK select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4
- select FSL_CAAM
- select FSL_BLOB
- select MISC
- select ARCH_MISC_INIT
- select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" @@ -81,6 +91,10 @@ config TARGET_IMX8MN_EVK select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4
- select FSL_CAAM
- select FSL_BLOB
- select MISC
- select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" @@ -88,6 +102,10 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8MN select SUPPORT_SPL select IMX8M_DDR4
- select FSL_CAAM
- select FSL_BLOB
- select MISC
- select SPL_CRYPTO if SPL
config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" @@ -95,6 +113,11 @@ config TARGET_IMX8MP_EVK select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4
- select FSL_CAAM
- select FSL_BLOB
- select MISC
- select ARCH_MISC_INIT
- select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach- imx/imx8m/soc.c index f2ddc834d4..0fe28f4971 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- Copyright 2017-2019 NXP
- Copyright 2017-2019, 2021 NXP
* * Peng Fan peng.fan@nxp.com */ @@ -20,6 +20,7 @@ #include <asm/ptrace.h> #include <asm/armv8/mmu.h> #include <dm/uclass.h> +#include <dm/device.h> #include <efi_loader.h> #include <env.h> #include <env_internal.h> @@ -1187,6 +1188,13 @@ static void acquire_buildinfo(void) int arch_misc_init(void) {
- struct udevice *dev;
- int ret;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
printf("Failed to initialize %s: %d\n", dev->name,ret);
acquire_buildinfo(); return 0; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 4ef7f6f180..c81128f442 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- Copyright 2019 NXP
- Copyright 2019, 2021 NXP
*/ #include <common.h> @@ -51,6 +51,13 @@ static void spl_dram_init(void) void spl_board_init(void) {
- struct udevice *dev;
- int ret;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
printf("Failed to initialize %s: %d\n", dev->name,ret);
puts("Normal Boot\n"); } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 03f2a56e80..ab19dabf7b 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /*
- Copyright 2018-2019 NXP
- Copyright 2018-2019, 2021 NXP
*
- SPDX-License-Identifier: GPL-2.0+
*/ #include <common.h> @@ -49,6 +49,10 @@ void spl_board_init(void) struct udevice *dev; int ret;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
printf("Failed to initialize %s: %d\n", dev->name,ret);
puts("Normal Boot\n"); ret = uclass_get_device_by_name(UCLASS_CLK, diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index a7564e9b1a..cf9a1235d5 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /*
- Copyright 2018-2019 NXP
- Copyright 2018-2019, 2021 NXP
*
- SPDX-License-Identifier: GPL-2.0+
*/ #include <common.h> @@ -20,6 +20,8 @@ #include <asm/arch/ddr.h> #include <power/pmic.h> #include <power/pca9450.h> +#include <dm/uclass.h> +#include <dm/device.h> DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +37,13 @@ void spl_dram_init(void) void spl_board_init(void) {
- struct udevice *dev;
- int ret;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
printf("Failed to initialize %s: %d\n", dev->name,ret);
/* * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does * not allow to change it. Should set the clock after PMIC diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index e8e0efe485..cdd17add08 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- Copyright 2018 NXP
- Copyright 2018, 2021 NXP
*
- SPDX-License-Identifier: GPL-2.0+
*/ #include <common.h> @@ -22,6 +21,7 @@ #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/mxc_i2c.h> #include <fsl_esdhc_imx.h> +#include <fsl_sec.h> #include <mmc.h> #include <linux/delay.h> #include <power/pmic.h> @@ -199,6 +199,11 @@ int power_init_board(void) void spl_board_init(void) { +#ifdef CONFIG_FSL_CAAM
- if (sec_init())
printf("\nsec_init failed!\n");+#endif puts("Normal Boot\n"); } diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index c5a8b0459e..1b027f253c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -43,9 +43,17 @@ struct udevice *caam_dev; #define SEC_ADDR(idx) \ (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) -#define SEC_JR0_ADDR(idx) \ +#ifndef CONFIG_IMX8M +#define SEC_JR_ADDR(idx) \ (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) +#define JR_ID 0 +#else +#define SEC_JR_ADDR(idx) \
- (ulong)(SEC_ADDR(idx) + \
- (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 1 +#endif struct caam_regs caam_st; #endif @@ -671,8 +679,8 @@ int sec_init_idx(uint8_t sec_idx) caam = dev_get_priv(caam_dev); #else caam_st.sec = (void *)SEC_ADDR(sec_idx);
- caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- caam_st.jrid = 0;
- caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx);
- caam_st.jrid = JR_ID;
caam = &caam_st; #endif #ifndef CONFIG_ARCH_IMX8 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d86f35856f..4f773198e3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2107,6 +2107,7 @@ CONFIG_SYS_FSL_IFC_SIZE2 CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_JR0_ADDR CONFIG_SYS_FSL_JR0_OFFSET +CONFIG_SYS_FSL_JR1_OFFSET CONFIG_SYS_FSL_LS1_CLK_ADDR CONFIG_SYS_FSL_LSCH3_SERDES_ADDR CONFIG_SYS_FSL_MAX_NUM_OF_SEC