On 10/16/18 1:23 AM, Alison Wang wrote:
I2C is used to access DDR SPD in the DDR initialization for SPL. In i2c_write process, get_timer() will be called. In board_init_f for SPL, timer_init() is not called before. The system counter is not enabled and the counter frequency is not set to 12.5MHz in SPL. The parameters for do_div() are zero too.
It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its own set of libgcc functions. As the parameters for do_div() are zero, __div0 will be called. Then the processor will stay in an endless loop after calling hang().
This patch will add timer_init() in board_init_f for SPL and fix a series of issues it caused.
Signed-off-by: Alison Wang alison.wang@nxp.com
This set is applied to fsl-qoriq master, awaiting upstream. Thanks.
York