On Sun, Apr 26, 2020 at 5:21 AM Shawn Lin shawn.lin@rock-chips.com wrote:
On 2020/4/25 19:03, Jagan Teki wrote:
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Thanks for your patches!
Signed-off-by: Patrick Wildt patrick@blueri.se Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_rockchip.c | 460 ++++++++++++++++++++++++++++++++++++ drivers/pci/pcie_rockchip.h | 79 +++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 437cd9a055..3dba84103b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -197,4 +197,12 @@ config PCIE_MEDIATEK Say Y here if you want to enable Gen2 PCIe controller, which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"select DM_PCIdefault y if ROCKCHIP_RK3399helpSay Y here if you want to enable PCIe controller support onRockchip SoCs.- endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c051ecc9f3..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c new file mode 100644 index 0000000000..adc64aedf5 --- /dev/null +++ b/drivers/pci/pcie_rockchip.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Rockchip AXI PCIe host controller driver
- Copyright (c) 2016 Rockchip, Inc.
- Copyright (c) 2020 Amarula Solutions(India)
- Copyright (c) 2020 Jagan Teki jagan@amarulasolutions.com
- Copyright (c) 2019 Patrick Wildt patrick@blueri.se
- Copyright (c) 2018 Mark Kettenis kettenis@openbsd.org
- Bits taken from Linux Rockchip PCIe host controller.
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <pci.h> +#include <power-domain.h> +#include <power/regulator.h> +#include <reset.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <linux/iopoll.h>
+#include "pcie_rockchip.h"
+DECLARE_GLOBAL_DATA_PTR;
+static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,enum pci_size_t size)+{
struct rockchip_pcie *priv = dev_get_priv(bus);ulong value;u32 off;off = (PCI_BUS(bdf) << 20) | (PCI_DEV(bdf) << 15) |(PCI_FUNC(bdf) << 12) | (offset & ~0x3);if ((PCI_BUS(bdf) == priv->first_busno) && (PCI_DEV(bdf) == 0)) {value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}if ((PCI_BUS(bdf) == priv->first_busno + 1) && (PCI_DEV(bdf) == 0)) {value = readl(priv->axi_base + off);*valuep = pci_conv_32_to_size(value, offset, size);return 0;}*valuep = pci_get_ff(size);PCIe cfg accessors, for instance, rockchip_pcie_rd_config，is supposed to configure TLP type to PCIE_ATR_HDR_CFG_TYPE1 if scanning the downstream buses, as it possiblely is a pcie-switch which should need forward the type1 header packets.
Linux driver is a good example for reference: https://elixir.bootlin.com/linux/latest/source/drivers/pci/controller/pcie-r...
Looks like we need to preserve root_bus_nr for this, but this indeed requires to parse the pcie ranges which I'm not sure it would be available in U-Boot. But, I can mark it as TODO if it really requires it in U-Boot.?
Jagan.