Hi Wolfgang,
On Monday 10 December 2007 13:04, you wrote:
Hi,
The observation is that using callbacks for every single data/clock line change takes very long, doing this in a monolithic function is much faster; additionally, you could take advantage of some hardware (e.g. SPI, although I did not get this to work yet) to do the actual load.
The new fwr callback makes sense to me. I agree that using the callbacks for every signal change might be very slow. I used the the slave parallel code to load an fpga in slave serial mode some time before. This reduces the callbacks a lot and booting was about 4 times faster. I used the byte write callback to shift out 8 bits in this case.
I hope that my FPGA patches will get it into U-Boot when the next merge windows opens. Perhaps you can provide a patch on top of that afterwards.
Matthias