On Monday 31 March 2008, M B wrote:
No. High and low *are* swapped. I just re-checked with users manual rev 1.08. GPIO0_OSRH has offset 0x0C and GPIO0_OSRL has offset 0x08. So this matches the offsets of all other 4xx GPIO registers I have seen so far.
You're right. This was fixed in v 1.06, so this explains why I and ppc405.h was wrong. btw. v1.10 of the Users Manual is out.
Thanks. I'll download right away.
I'm not really sure if this is true though since Taihu is using gpio_set_chip_configuration() without known problems. Could you please re-check with AMCC support, if this statement for 405EP is correct? If this pin assignment of the 405EP GPIO block is incompatible with other GPIO cores, like the one on 440EP or 405EX.
I will do. All ppc405 which used the CFG_GPIO0_*{H,L} defines in their config file were using the "wrong" address.
No. 405EX & 405EZ which were added recently are using the correct addresses.
Best regards, Stefan
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