Re: [PATCH] imx: imx8mp: Add support for Polyhex Debix Model A SBC

Hi Peng,

Le jeu. 11 mai 2023 à 20:47, Peng Fan peng.fan@oss.nxp.com a écrit :

Hi Gilles,

only some minor comments, overall looks good.

Thanks for the review. Will fix all comments, but one (see below).

On 4/13/2023 9:17 PM, Gilles Talis wrote:

...

Add support for the Polyhex Debix Model A SBC board. It is an industrial grade single board computer based on NXP's i.MX 8M Plus. Currently supported interfaces are:

• Serial console
• Micro SD
• eQOS and FEC Ethernet

imx8mp-debix-model-a.dts is taken from Linux 6.3-rc6.

Signed-off-by: Gilles Talis gilles.talis@gmail.com

arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi | 140 ++ arch/arm/dts/imx8mp-debix-model-a.dts | 507 +++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/polyhex/imx8mp_debix_model_a/Kconfig | 15 + .../polyhex/imx8mp_debix_model_a/MAINTAINERS | 8 + board/polyhex/imx8mp_debix_model_a/Makefile | 12 + .../imx8mp_debix_model_a.c | 54 + .../imximage-8mp-lpddr4.cfg | 9 + .../imx8mp_debix_model_a/lpddr4_timing.c | 1843 +++++++++++++++++ board/polyhex/imx8mp_debix_model_a/spl.c | 129 ++ configs/imx8mp_debix_model_a_defconfig | 110 + include/configs/imx8mp_debix_model_a.h | 54 + 13 files changed, 2890 insertions(+) create mode 100644 arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts create mode 100644 board/polyhex/imx8mp_debix_model_a/Kconfig create mode 100644 board/polyhex/imx8mp_debix_model_a/MAINTAINERS create mode 100644 board/polyhex/imx8mp_debix_model_a/Makefile create mode 100644 board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c create mode 100644 board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg create mode 100644 board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c create mode 100644 board/polyhex/imx8mp_debix_model_a/spl.c create mode 100644 configs/imx8mp_debix_model_a_defconfig create mode 100644 include/configs/imx8mp_debix_model_a.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 337bee7e1e..5e1dd627d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -997,6 +997,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \

• imx8mp-debix-model-a.dtb \
  imx8mp-dhcom-pdk2.dtb \
  imx8mp-dhcom-pdk3.dtb \
  imx8mp-evk.dtb \
  

diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi new file mode 100644 index 0000000000..97c011895f --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright 2019, 2021 NXP

Need update time?

...

• */

+#include "imx8mp-u-boot.dtsi"

[.....]

...

index 0000000000..58dae612b4 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a.dts @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright 2019 NXP
• • Copyright 2022 Ideas on Board Oy

Time?

This was taken as is from the kernel. Hence, the reason why the date is unchanged.

...

• */

+/dts-v1/;

+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/usb/pd.h>

+#include "imx8mp.dtsi"

[....]

...

diff --git a/board/polyhex/imx8mp_debix_model_a/Makefile b/board/polyhex/imx8mp_debix_model_a/Makefile new file mode 100644 index 0000000000..dffaccedb8 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2019 NXP

Time?

...

+# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += imx8mp_debix_model_a.o

+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c new file mode 100644 index 0000000000..ff73510ad6 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright 2019 NXP

Ditto

...

• */

+#include <common.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <miiphy.h> +#include <netdev.h> +#include <linux/delay.h> +#include <asm/global_data.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h>

Sort the headers

...

+DECLARE_GLOBAL_DATA_PTR;

+static void setup_fec(void) +{

• struct iomuxc_gpr_base_regs *gpr =
  

•         (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  

• /* Enable RGMII TX clk output */
  

• setbits_le32(&gpr->gpr[1], BIT(22));
  

+}

+#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{

• if (phydev->drv->config)
  

•         phydev->drv->config(phydev);
  

• return 0;
  

+} +#endif

+int board_init(void) +{

• int ret = 0;
  

• if (IS_ENABLED(CONFIG_FEC_MXC))
  

•         setup_fec();
  

• return ret;
  

+}

+int board_late_init(void) +{

• return 0;
  

+} diff --git a/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..6dedf1724a --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright 2021 NXP

Time

...

• */

+ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c new file mode 100644 index 0000000000..8f76aa3728 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c @@ -0,0 +1,1843 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright 2019 NXP

Ditto

...

• */

...

+};

+struct dram_fsp_msg ddr_dram_fsp_msg[] = {

• {
  

•         /* P0 3732mts 1D */
  

•         .drate = 3732,
  

•         .fw_type = FW_1D_IMAGE,
  

•         .fsp_cfg = ddr_fsp0_cfg,
  

•         .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
  

• },
  

• {
  

•         /* P1 400mts 1D */
  

•         .drate = 400,
  

•         .fw_type = FW_1D_IMAGE,
  

•         .fsp_cfg = ddr_fsp1_cfg,
  

•         .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
  

• },
  

• {
  

•         /* P2 100mts 1D */
  

•         .drate = 100,
  

•         .fw_type = FW_1D_IMAGE,
  

•         .fsp_cfg = ddr_fsp2_cfg,
  

•         .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
  

• },
  

• {
  

•         /* P0 3732mts 2D */
  

•         .drate = 3732,
  

•         .fw_type = FW_2D_IMAGE,
  

•         .fsp_cfg = ddr_fsp0_2d_cfg,
  

•         .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
  

• },
  

+};

+/* ddr timing config params */ +struct dram_timing_info dram_timing = {

• .ddrc_cfg = ddr_ddrc_cfg,
  

• .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
  

• .ddrphy_cfg = ddr_ddrphy_cfg,
  

• .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
  

• .fsp_msg = ddr_dram_fsp_msg,
  

• .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
  

• .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
  

• .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
  

• .ddrphy_pie = ddr_phy_pie,
  

• .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
  

• .fsp_table = { 3732, 400, 100, },
  

+};

diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c new file mode 100644 index 0000000000..9b522e8d9c --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*

• • Copyright 2018-2019, 2021 NXP
• • Copyright 2023 Gilles Talis gilles.talis@gmail.com > + *

Blank line.

...

• */

+#include <common.h> +#include <hang.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/arch/ddr.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <dm/uclass.h> +#include <dm/device.h>

Sort headers

...

+DECLARE_GLOBAL_DATA_PTR;

+int spl_board_boot_device(enum boot_device boot_dev_spl) +{

• return BOOT_DEVICE_BOOTROM;
  

+}

+void spl_dram_init(void) +{

• ddr_init(&dram_timing);
  

+}

+void spl_board_init(void) +{

• /*
  

•  * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
  

•  * not allow to change it. Should set the clock after PMIC
  

•  * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
  

•  * set by ROM for ND VDD_SOC
  

•  */
  

• clock_enable(CCGR_GIC, 0);
  

• clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
  

• clock_enable(CCGR_GIC, 1);
  

• puts("Normal Boot\n");
  

+}

+static int power_init_board(void) +{

• struct udevice *dev;
  

• int ret;
  

• ret = pmic_get("pmic@25", &dev);
  

• if (ret == -ENODEV) {
  

•         puts("Failed to get PMIC\n");
  

•         return 0;
  

• }
  

• if (ret != 0)
  

•         return ret;
  

• /* BUCKxOUT_DVS0/1 control BUCK123 output. */
  

• pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
  

• /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
  

• if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
  

•         /* Set DVS0 to 0.85V for special case. */
  

•         pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
  

• else
  

•         pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
  

• /* Set DVS1 to 0.85v for suspend. */
  

• pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
  

• /*
  

•  * Enable DVS control through PMIC_STBY_REQ and
  

•  * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
  

•  */
  

• pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
  

• /*
  

•  * Kernel uses OD/OD frequency for SoC.
  

•  * To avoid timing risk from SoC to ARM,
  

•  * increase VDD_ARM to OD voltage 0.95V
  

•  */
  

• pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
  

• return 0;
  

+}

+int board_fit_config_name_match(const char *name) +{

• if (is_imx8mp() &&
  

•     !strcmp(name, "imx8mp-debix-model-a"))
  

•         return 0;
  

• return -1;
  

+}

+void board_init_f(ulong dummy) +{

• int ret;
  

• arch_cpu_init();
  

• init_uart_clk(1);
  

• /* Clear the BSS. */
  

• memset(__bss_start, 0, __bss_end - __bss_start);
  

• ret = spl_init();
  

• if (ret) {
  

•         debug("spl_init() failed: %d\n", ret);
  

•         hang();
  

• }
  

• preloader_console_init();
  

• enable_tzc380();
  

• power_init_board();
  

• /* DDR initialization */
  

• spl_dram_init();
  

• board_init_r(NULL, 0);
  

+} diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig new file mode 100644 index 0000000000..5de80233bd --- /dev/null +++ b/configs/imx8mp_debix_model_a_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-debix-model-a.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h new file mode 100644 index 0000000000..e82e8b16b1 --- /dev/null +++ b/include/configs/imx8mp_debix_model_a.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright 2019 NXP
• • Copyright 2023 Gilles Talis gilles.talis@gmail.com
• */

+#ifndef __IMX8MP_DEBIX_MODEL_A_H +#define __IMX8MP_DEBIX_MODEL_A_H

+#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h>

+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)

+#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 1

+#define PHY_ANEG_TIMEOUT 20000

+#endif

+#define BOOT_TARGET_DEVICES(func) \

• func(MMC, mmc, 1) \
  

• func(MMC, mmc, 2)
  

+#include <config_distro_bootcmd.h>

+/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \

• BOOTENV \
  

• "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  

• "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  

• "image=Image\0" \
  

• "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  

• "fdt_addr_r=0x43000000\0"                       \
  

• "boot_fdt=try\0" \
  

• "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  

• "initrd_addr=0x43800000\0"              \
  

• "bootm_size=0x10000000\0" \
  

• "mmcpart=1\0" \
  

• "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  

+/* Link Definitions */

+#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000

+/* 2GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */

+#endif

Regards, Peng.

Regards Gilles.