The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@altera.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Pavel Machek pavel@denx.de Acked-by: Pavel Machek pavel@denx.de --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 54343b8..76979b1 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -26,6 +26,8 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS
+#define CONFIG_SYS_CACHELINE_SIZE 32 + /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040