Add device tree for N5X.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/dts/Makefile | 1 + ..._agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++-- .../dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} | 90 +++++++++++++--------- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 ++++++++++++++++ ...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 10 ++- 5 files changed, 135 insertions(+), 46 deletions(-) copy arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%) copy arch/arm/dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} (88%) create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (92%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c6710826a0..7443fde97d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -380,6 +380,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi similarity index 85% copy from arch/arm/dts/socfpga_agilex-u-boot.dtsi copy to arch/arm/dts/socfpga_n5x-u-boot.dtsi index 08f7cf7f7a..7ded8ceb9a 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
#include "socfpga_soc64_fit-u-boot.dtsi" @@ -53,6 +53,10 @@ reset-names = "i2c"; };
+&memclkmgr { + u-boot,dm-pre-reloc; +}; + &mmc { resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; }; @@ -76,11 +80,10 @@ };
&sdr { - compatible = "intel,sdr-ctl-agilex"; - reg = <0xf8000400 0x80>, - <0xf8010000 0x190>, - <0xf8011000 0x500>; + compatible = "intel,sdr-ctl-dm"; resets = <&rst DDRSCH_RESET>; + clocks = <&memclkmgr>; + clock-names = "mem_clk"; u-boot,dm-pre-reloc; };
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_n5x.dtsi similarity index 88% copy from arch/arm/dts/socfpga_agilex.dtsi copy to arch/arm/dts/socfpga_n5x.dtsi index c3ead2d72b..984524c79a 100644 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ b/arch/arm/dts/socfpga_n5x.dtsi @@ -1,15 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2020-2021, Intel Corporation */
/dts-v1/; #include <dt-bindings/reset/altr,rst-mgr-s10.h> #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/agilex-clock.h> +#include <dt-bindings/clock/n5x-clock.h>
/ { - compatible = "intel,socfpga-agilex"; + compatible = "intel,socfpga-n5x"; #address-cells = <2>; #size-cells = <2>;
@@ -103,7 +103,7 @@ };
clkmgr: clock-controller@ffd10000 { - compatible = "intel,agilex-clkmgr"; + compatible = "intel,n5x-clkmgr"; reg = <0xffd10000 0x1000>; #clock-cells = <1>; }; @@ -124,6 +124,11 @@ compatible = "fixed-clock"; };
+ dram_eosc_clk: dram-eosc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -136,7 +141,9 @@ }; }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac", + "snps,dwmac-3.74a", + "snps,dwmac"; reg = <0xff800000 0x2000>; interrupts = <0 90 4>; interrupt-names = "macirq"; @@ -148,13 +155,15 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 1>; altr,sysmgr-syscon = <&sysmgr 0x44 0>; - clocks = <&clkmgr AGILEX_EMAC0_CLK>; + clocks = <&clkmgr N5X_EMAC0_CLK>; clock-names = "stmmaceth"; status = "disabled"; };
gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac", + "snps,dwmac-3.74a", + "snps,dwmac"; reg = <0xff802000 0x2000>; interrupts = <0 91 4>; interrupt-names = "macirq"; @@ -166,13 +175,15 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 2>; altr,sysmgr-syscon = <&sysmgr 0x48 8>; - clocks = <&clkmgr AGILEX_EMAC1_CLK>; + clocks = <&clkmgr N5X_EMAC1_CLK>; clock-names = "stmmaceth"; status = "disabled"; };
gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac", + "snps,dwmac-3.74a", + "snps,dwmac"; reg = <0xff804000 0x2000>; interrupts = <0 92 4>; interrupt-names = "macirq"; @@ -184,7 +195,7 @@ snps,multicast-filter-bins = <256>; iommus = <&smmu 3>; altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - clocks = <&clkmgr AGILEX_EMAC2_CLK>; + clocks = <&clkmgr N5X_EMAC2_CLK>; clock-names = "stmmaceth"; status = "disabled"; }; @@ -236,7 +247,7 @@ reg = <0xffc02800 0x100>; interrupts = <0 103 4>; resets = <&rst I2C0_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
@@ -247,7 +258,7 @@ reg = <0xffc02900 0x100>; interrupts = <0 104 4>; resets = <&rst I2C1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
@@ -258,7 +269,7 @@ reg = <0xffc02a00 0x100>; interrupts = <0 105 4>; resets = <&rst I2C2_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
@@ -269,7 +280,7 @@ reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; resets = <&rst I2C3_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
@@ -280,10 +291,17 @@ reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; resets = <&rst I2C4_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
+ memclkmgr: mem-clock-controller@f8040000 { + compatible = "intel,n5x-mem-clkmgr"; + reg = <0xf8040000 0x1000>; + #clock-cells = <0>; + clocks = <&dram_eosc_clk>, <&f2s_free_clk>; + }; + mmc: dwmmc0@ff808000 { #address-cells = <1>; #size-cells = <0>; @@ -293,8 +311,8 @@ fifo-depth = <0x400>; resets = <&rst SDMMC_RESET>; reset-names = "reset"; - clocks = <&clkmgr AGILEX_L4_MP_CLK>, - <&clkmgr AGILEX_SDMMC_CLK>; + clocks = <&clkmgr N5X_L4_MP_CLK>, + <&clkmgr N5X_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; status = "disabled"; @@ -334,13 +352,13 @@ #dma-requests = <32>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + clocks = <&clkmgr N5X_L4_MAIN_CLK>; clock-names = "apb_pclk"; };
rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; + compatible = "altr,rst-mgr"; reg = <0xffd11000 0x100>; };
@@ -366,8 +384,7 @@ };
spi0: spi@ffda4000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + compatible = "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda4000 0x1000>; @@ -375,13 +392,12 @@ resets = <&rst SPIM0_RESET>; reg-io-width = <4>; num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + clocks = <&clkmgr N5X_L4_MAIN_CLK>; status = "disabled"; };
spi1: spi@ffda5000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + compatible = "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda5000 0x1000>; @@ -389,7 +405,7 @@ resets = <&rst SPIM1_RESET>; reg-io-width = <4>; num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + clocks = <&clkmgr N5X_L4_MAIN_CLK>; status = "disabled"; };
@@ -411,7 +427,7 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 113 4>; reg = <0xffc03000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; clock-names = "timer"; };
@@ -419,7 +435,7 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 114 4>; reg = <0xffc03100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; clock-names = "timer"; };
@@ -427,7 +443,7 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 115 4>; reg = <0xffd00000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; clock-names = "timer"; };
@@ -435,7 +451,7 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 116 4>; reg = <0xffd00100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; clock-names = "timer"; };
@@ -447,7 +463,7 @@ reg-io-width = <4>; resets = <&rst UART0_RESET>; status = "disabled"; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; clock-frequency = <100000000>; };
@@ -458,7 +474,7 @@ reg-shift = <2>; reg-io-width = <4>; resets = <&rst UART1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clocks = <&clkmgr N5X_L4_SP_CLK>; status = "disabled"; };
@@ -476,7 +492,7 @@ phy-names = "usb2-phy"; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr AGILEX_USB_CLK>; + clocks = <&clkmgr N5X_USB_CLK>; iommus = <&smmu 6>; status = "disabled"; }; @@ -490,7 +506,7 @@ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; iommus = <&smmu 7>; - clocks = <&clkmgr AGILEX_USB_CLK>; + clocks = <&clkmgr N5X_USB_CLK>; status = "disabled"; };
@@ -499,7 +515,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; status = "disabled"; };
@@ -508,7 +524,7 @@ reg = <0xffd00300 0x100>; interrupts = <0 118 4>; resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; status = "disabled"; };
@@ -517,7 +533,7 @@ reg = <0xffd00400 0x100>; interrupts = <0 125 4>; resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; status = "disabled"; };
@@ -526,7 +542,7 @@ reg = <0xffd00500 0x100>; interrupts = <0 126 4>; resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; status = "disabled"; };
diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi new file mode 100644 index 0000000000..57509f083e --- /dev/null +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + */ + +#include "socfpga_n5x-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + }; + + memory { + /* + * Memory type: DDR4 + * 16GB + * <0 0x00000000 0 0x80000000>, + * <4 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <2 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <1 0x80000000 0 0x80000000>; + * + * Memory type: LPDDR4 (non-interleaving mode) + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure + * region. + */ + reg = <0 0x00000000 0 0x60000000>, + <0x10 0x00100000 0 0x40000000>; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&i2c1 { + status = "okay"; +}; + +&nand { + u-boot,dm-pre-reloc; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts similarity index 92% copy from arch/arm/dts/socfpga_agilex_socdk.dts copy to arch/arm/dts/socfpga_n5x_socdk.dts index bcdeecc0e0..bf74414c9e 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_n5x_socdk.dts @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2020-2021, Intel Corporation */ -#include "socfpga_agilex.dtsi" +#include "socfpga_n5x.dtsi"
/ { - model = "SoCFPGA Agilex SoCDK"; + model = "SoCFPGA N5X SoCDK";
aliases { serial0 = &uart0; @@ -16,6 +16,7 @@
chosen { stdout-path = "serial0:115200n8"; + u-boot,boot0 = <&mmc>; };
leds { @@ -106,6 +107,7 @@ };
&qspi { + status = "okay"; flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -116,7 +118,7 @@ m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; - cdns,read-delay = <1>; + cdns,read-delay = <3>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>;