Hi York,
This patch is to adjust the OOB (out of bound) timing of sata port. It is totally hardware timing. I was asked to update those timing by hardware/validation team. They calculated those values from clock frequency. You can apply it safely.
Please apply this patch with SATA added.
Thanks, Andy
-----Original Message----- From: York Sun Sent: Tuesday, December 05, 2017 12:47 AM To: Andy Tang andy.tang@nxp.com Cc: albert.u.boot@aribaud.net; sjg@chromium.org; u-boot@lists.denx.de Subject: Re: [PATCH] armv8: layerscape: refine port register configuration
On 12/04/2017 01:31 AM, Yuantian Tang wrote:
These PP2C and PP3C registers control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively
for
sata port. Overwrite default values with calculated ones to get better OOB timing.
Signed-off-by: Tang Yuantian andy.tang@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++ 2 files changed, 8 insertions(+)
Andy,
Maybe it was obvious to you, but I couldn't understand why and what you are changing, except you overwrite two registers.
By the way, you may want to add SATA (in upper case) in the subject.
York