Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

On 7/18/22 11:10 AM, Andre Przywara wrote:

On Wed, 13 Jul 2022 22:15:21 -0500 Samuel Holland samuel@sholland.org wrote:

Hi,

...

Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model.

The bit locations are copied from the Linux CCU drivers.

Signed-off-by: Samuel Holland samuel@sholland.org

drivers/clk/sunxi/clk_a10.c | 2 ++ drivers/clk/sunxi/clk_a10s.c | 2 ++ drivers/clk/sunxi/clk_a23.c | 3 +++ drivers/clk/sunxi/clk_a31.c | 6 ++++++ drivers/clk/sunxi/clk_a64.c | 3 +++ drivers/clk/sunxi/clk_a80.c | 8 ++++++++ drivers/clk/sunxi/clk_a83t.c | 3 +++ drivers/clk/sunxi/clk_h3.c | 3 +++ drivers/clk/sunxi/clk_h6.c | 6 ++++++ drivers/clk/sunxi/clk_h616.c | 6 ++++++ drivers/clk/sunxi/clk_r40.c | 3 +++ 11 files changed, 45 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index db92848aafde..69c46da841e9 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), [CLK_AHB_MMC3] = GATE(0x060, BIT(11)),

• [CLK_AHB_NAND] = GATE(0x060, BIT(13)), [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),

@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_APB1_UART6] = GATE(0x06c, BIT(22)), [CLK_APB1_UART7] = GATE(0x06c, BIT(23)),

• [CLK_NAND] = GATE(0x080, BIT(31)), [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)), [CLK_SPI2] = GATE(0x0a8, BIT(31)),

diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 0c6564ef3b62..6abccea3aa9e 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),

• [CLK_AHB_NAND] = GATE(0x060, BIT(13)), [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),

@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), [CLK_APB1_UART3] = GATE(0x06c, BIT(19)),

• [CLK_NAND] = GATE(0x080, BIT(31)), [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)), [CLK_SPI2] = GATE(0x0a8, BIT(31)),

diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 0280fb51e2db..342af83b158d 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),

• [CLK_BUS_NAND] = GATE(0x060, BIT(13)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),

@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),

• [CLK_NAND] = GATE(0x080, BIT(31)), [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)),

@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),

• [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 26d25f324080..703ddc01dad0 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),

• [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)),
• [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)), [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),

@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_APB2_UART4] = GATE(0x06c, BIT(20)), [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),

• [CLK_NAND0] = GATE(0x080, BIT(31)),
• [CLK_NAND1] = GATE(0x084, BIT(31)), [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)), [CLK_SPI2] = GATE(0x0a8, BIT(31)),

@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = { [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),

• [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)),
• [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)), [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)), [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)), [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index cbb9168edb9c..916ff4c2b5d1 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),

• [CLK_BUS_NAND] = GATE(0x060, BIT(13)), [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),

@@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),

• [CLK_NAND] = GATE(0x080, BIT(31)), [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)),

@@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),

• [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 1ee1f99a8f49..be732f5d1b50 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -14,12 +14,18 @@ #include <linux/bitops.h>

static const struct ccu_clk_gate a80_gates[] = {

• [CLK_NAND0_0] = GATE(0x400, BIT(31)),
• [CLK_NAND0_1] = GATE(0x404, BIT(31)),
• [CLK_NAND1_0] = GATE(0x408, BIT(31)),
• [CLK_NAND1_1] = GATE(0x40c, BIT(31)),

So my copy of the manual (v1.1 from the Wiki) doesn't have the second pair, although there are two gates, so I assume it's just a doc issue.

...

[CLK_SPI0] = GATE(0x430, BIT(31)), [CLK_SPI1] = GATE(0x434, BIT(31)), [CLK_SPI2] = GATE(0x438, BIT(31)), [CLK_SPI3] = GATE(0x43c, BIT(31)),

[CLK_BUS_MMC] = GATE(0x580, BIT(8)),

• [CLK_BUS_NAND0] = GATE(0x580, BIT(12)),
• [CLK_BUS_NAND1] = GATE(0x580, BIT(13)),

Those seem to be swapped, in line with the other dual NAND SoCs.

...

[CLK_BUS_SPI0] = GATE(0x580, BIT(20)), [CLK_BUS_SPI1] = GATE(0x580, BIT(21)), [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), @@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gates[] = {

static const struct ccu_reset a80_resets[] = { [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),

• [RST_BUS_NAND0] = RESET(0x5a0, BIT(12)),
• [RST_BUS_NAND1] = RESET(0x5a0, BIT(13)),

and those two as well.

Compared the rest against the respective manuals, they look fine.

Indeed, the manual has them swapped. Then that means the Linux driver is also wrong. I will send a patch for it.

Regards, Samuel