Add device tree for N5X.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
--- v2: - Remove socfpga_n5x.dtsi - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update n5x data accordingly. --- arch/arm/dts/Makefile | 1 + ...ex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 +++++++++++ ...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 110 +++++++++++++++++- 4 files changed, 182 insertions(+), 9 deletions(-) copy arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%) create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (57%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aec5020a0f..2e13277816 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi similarity index 85% copy from arch/arm/dts/socfpga_agilex-u-boot.dtsi copy to arch/arm/dts/socfpga_n5x-u-boot.dtsi index 08f7cf7f7a..2f63f4a4e6 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
#include "socfpga_soc64_fit-u-boot.dtsi" @@ -53,6 +53,10 @@ reset-names = "i2c"; };
+&memclkmgr { + u-boot,dm-pre-reloc; +}; + &mmc { resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; }; @@ -76,11 +80,10 @@ };
&sdr { - compatible = "intel,sdr-ctl-agilex"; - reg = <0xf8000400 0x80>, - <0xf8010000 0x190>, - <0xf8011000 0x500>; + compatible = "intel,sdr-ctl-n5x"; resets = <&rst DDRSCH_RESET>; + clocks = <&memclkmgr>; + clock-names = "mem_clk"; u-boot,dm-pre-reloc; };
diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi new file mode 100644 index 0000000000..57509f083e --- /dev/null +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + */ + +#include "socfpga_n5x-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + }; + + memory { + /* + * Memory type: DDR4 + * 16GB + * <0 0x00000000 0 0x80000000>, + * <4 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <2 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <1 0x80000000 0 0x80000000>; + * + * Memory type: LPDDR4 (non-interleaving mode) + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure + * region. + */ + reg = <0 0x00000000 0 0x60000000>, + <0x10 0x00100000 0 0x40000000>; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&i2c1 { + status = "okay"; +}; + +&nand { + u-boot,dm-pre-reloc; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts similarity index 57% copy from arch/arm/dts/socfpga_agilex_socdk.dts copy to arch/arm/dts/socfpga_n5x_socdk.dts index bcdeecc0e0..30130bb910 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_n5x_socdk.dts @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2020-2021, Intel Corporation */ #include "socfpga_agilex.dtsi" +#include <dt-bindings/clock/n5x-clock.h>
/ { - model = "SoCFPGA Agilex SoCDK"; + model = "eASIC N5X SoCDK";
aliases { serial0 = &uart0; @@ -16,6 +17,7 @@
chosen { stdout-path = "serial0:115200n8"; + u-boot,boot0 = <&mmc>; };
leds { @@ -47,10 +49,26 @@ osc1 { clock-frequency = <25000000>; }; + + dram_eosc_clk: dram-eosc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + }; + + memclkmgr: mem-clock-controller@f8040000 { + compatible = "intel,n5x-mem-clkmgr"; + reg = <0xf8040000 0x1000>; + #clock-cells = <0>; + clocks = <&dram_eosc_clk>, <&f2s_free_clk>; }; }; };
+&clkmgr { + compatible = "intel,n5x-clkmgr"; +}; + &gpio1 { status = "okay"; }; @@ -59,8 +77,8 @@ status = "okay"; phy-mode = "rgmii"; phy-handle = <&phy0>; - max-frame-size = <9000>; + clocks = <&clkmgr N5X_EMAC0_CLK>;
mdio0 { #address-cells = <1>; @@ -85,27 +103,111 @@ }; };
+&gmac1 { + clocks = <&clkmgr N5X_EMAC1_CLK>; +}; + +&gmac2 { + clocks = <&clkmgr N5X_EMAC2_CLK>; +}; + +&i2c0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&i2c1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&i2c2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&i2c3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&i2c4 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + &mmc { status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; + + clocks = <&clkmgr N5X_L4_MP_CLK>, + <&clkmgr N5X_SDMMC_CLK>; +}; + +&pdma { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&spi0 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&spi1 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&timer0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; };
&uart0 { status = "okay"; + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&uart1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; };
&usb0 { status = "okay"; + clocks = <&clkmgr N5X_USB_CLK>; disable-over-current; };
+&usb1 { + status = "okay"; + clocks = <&clkmgr N5X_USB_CLK>; +}; + &watchdog0 { status = "okay"; + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog1 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog2 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog3 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
&qspi { + status = "okay"; flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -116,7 +218,7 @@ m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; - cdns,read-delay = <1>; + cdns,read-delay = <3>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>;