This is for new platform enablement for agilex5. Add reset driver for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/reset/reset-socfpga.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 6e3f03e248..8b35f0685d 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -24,9 +24,18 @@ #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> - -#define BANK_INCREMENT 4 -#define NR_BANKS 8 +#include <asm/arch/reset_manager.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 +#define RSTMGR_PER0MODRST_USB31 BIT(4) +#define RSTMGR_PER0MODRST_NAND BIT(5) +#define RSTMGR_PER0MODRST_DMA BIT(16) +#define RSTMGR_PER0MODRST_DMAIF GENMASK(31, 24) +#define RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT RSTMGR_PER0MODRST_USB31 \ + | RSTMGR_PER0MODRST_NAND \ + | RSTMGR_PER0MODRST_DMA \ + | RSTMGR_PER0MODRST_DMAIF
struct socfpga_reset_data { void __iomem *modrst_base; @@ -112,9 +121,22 @@ static int socfpga_reset_remove(struct udevice *dev) { struct socfpga_reset_data *data = dev_get_priv(dev);
+/* + * TODO: This is temporary solution for NAND/DMA/USB3.1 deaasert. + * When NAND/DMA/USB3.1 driver is ready, the deassert shall be done + * from NAND/DMA/USB3.1 driver. + */ +#if defined(CONFIG_TARGET_SOCFPGA_AGILEX5) + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST, + RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT); +#endif + if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif }
return 0;