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On 05/12/2013 05:08 PM, Peter Korsgaard wrote:
"Tom" == Tom Rini trini@ti.com writes:
Tom> Due to hardware design, we can't have NAND present (as we know of NAND Tom> today) when booting from SPI, so disable NAND then as that simplifies Tom> logic.
Sorry, this description is not clear to me. I didn't check in detail, but as far as I remember the default pins for spi0 don't conflict with gmpc.
It's also not quite clear to me if you refer to SW support fo NAND flash or the hardware component when you say 'NAND' above.
OK, good point. I'm talking about HW support, and it should be spelled put better. Note that we're talking about the TI GP EVM, EVM SK, BeagleBone White and BeagleBone Black here, and not custom hardware. The EVM SK does not allow for expansion such as adding NAND/NOR flash and probably not SPI. The GP EVM can have only one of NOR, NAND or SPI flash active based on the profile that is selected for the whole hardware stack. The BeagleBone White may have a "memory cape" installed which in turn can have a NAND, NOR or eMMC board plugged into it. It's not impossible someone could come up with a SPI flash cape and plug the memory cape into that, or come up with a complex breadboard solution. But lets see that happen and work before worrying about that particular permutation.
- -- Tom