On 11/17/2017 05:43 PM, York Sun wrote:
On 09/12/2017 10:09 AM, Marek Vasut wrote:
The status register is optional in the AMD command sets, but it's presence can be checked by reading out CFI table entry 0xc bit 0. If the register is present, prefer using it's bit 7 to determine if the flash is busy over reading the flash ; this is needed ie. on Hyperflash memories.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
Marek,
Some of our boards failed. I traced to this commit. Reverting this commit fixes the issue. I happen to have two boards with slightly different flash chip. One works and the other doesn't.
I can't since I don't have the board with such a chip ... Which chip is that ? Mine is Spansion S25KL256 hyperflash.
The working board has
=> fli
Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801 Erase timeout: 2048 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 512 bytes
The failing board has
=> fli
Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes
Can you investigate?
York