On Wednesday, August 19, 2015 at 07:55:14 AM, Chin Liang See wrote:
Remove hard-coded SDMMC timing parameter drvsel and smplsel. This setting now will come from SDMMC calibration
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Stefan Roese sr@denx.de Cc: Tom Rini trini@konsulko.com
include/configs/socfpga_common.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5ca45a9..1ca795c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -155,8 +155,6 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
I believe this is pulled from DT nowaways, so feel free to send a separate patch to remove this from here and README.socfpga.
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
Certainly, I agree, this horribleness should go away.
/* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
Now that you're digging in the SD/MMC stuff -- is this still relevant at all? I don't think so, so you should be able to remove this as well (again, in a separate patch and with a sufficient amount of testing).
Best regards, Marek Vasut