[PATCH 1/1] riscv: remove cache enablement in start.S

Cache could be enabled in harts_early_init board-specific hook, so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang ycliang@andestech.com --- arch/riscv/cpu/start.S | 4 ---- 1 file changed, 4 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a9e1935692..8e58f641f1 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -210,10 +210,6 @@ wait_for_gd_init: bnez s2, secondary_hart_loop #endif

- /* Enable cache */ - jal icache_enable - jal dcache_enable - #ifdef CONFIG_DEBUG_UART jal debug_uart_init #endif