This series adds support for samus, the Chromebook Pixel 2015. Since it is only the second board added that does not use an FSP, there is quite a bit of refactoring involved to avoid code duplication.
Samus uses roughly the same binary blobs as link, except now there is one more called the reference code binary. The only available binary for this is a coreboot 'rmodule' extracted from flash. This is a simplified ELF format so it fairly easy to load and use.
It is also possible to boot U-Boot from coreboot on samus. This works well but for a delay for non-existent IDE on start-up. The standard build does not work with binaries taken from flash, so it isn't easy to replicate this - you'll just have to take my word for it. I am working on getting that figured out - coreboot recently gained upstream support for loading U-Boot as a payload, so it should be possible to get this working nicely before long.
In any case much of the code comes from coreboot - individual files are credited with their source.
Perhaps the main value of this series is the improved non-FSP support and additions for broadwell, which samus uses. It should make it easier to add support for future non-FSP platforms.
Changes in v2: - Use a #define for the output flush command - Adjust the code order slightly - Simplify the code in serial_initialize() - Use gd->arch.x86_mask to get the stepping value - Rename microcode_intel.c to microcode.c - Use capitals for header guard - Use capitals for header guard - Move cougarcanyon lpc_common.h include to this patch - Use capitals for header guard - Use capitals for header guard - Rename sdram_common.c to mrc.c - Rename sdram to mrc - Use setio_32() instead of setio_le32(), etc. - Add Kconfig help for the moved options - Fix tab indentation - Don't try to read microcode version on quark - Use gd->arch.x86_device instead of reading the device ID again - Rename subject to 'core' instead of 'code' - Fix micrcode typo - Don't try to update microcode on FSP platforms - Add GPIO output definition for a1 and a6 - Use setio_32() instead of setio_le32(), etc. - Fix 'PCB' typo (should be 'PCH') - Use setio_32() instead of setio_le32(), etc. - Use capitals for header guard - Use capitals for header guard - Use capitals for header guard - Fix comment style - Use capitals for header guard - Rename sdram to mrc - Use setio_32() instead of setio_le32(), etc. - Fix 'configure' typo - Correct naming of Intel platforms
Simon Glass (51): dm: timer: Correct timer init ordering after relocation arm: Add a 64-bit division routine to the private library dhry: Correct dhrystone calculation for fast machines syscon: Avoid returning a device on failure input: i8042: Make sure the keyboard is enabled x86: Allow use of serial soon after relocation x86: cpu: Add functions to return the family and stepping x86: Move cache-as-RAM code into a common location x86: Move microcode code to a common location x86: Create a common header for Intel register access x86: Add the root-complex block to common intel registers x86: Move common LPC code to its own place x86: Move common CPU code to its own place x86: Rename PORT_RESET to IO_PORT_RESET x86: Move Intel Management Engine code to a common place x86: ivybridge: Drop sandybridge_early_init() x86: Move common PCH code into a common place x86: Add common SDRAM-init code x86: ivybridge: Convert to use the common SDRAM code x86: dts: Drop memory SPD compatible string x86: Add macros to clear and set I/O bits x86: Allow I/O functions to use pointers x86: Move common MRC Kconfig options to the common file x86: Record the CPU details when starting each core x86: ivybridge: Show microcode version for each core x86: Update microcode for secondary CPUs x86: link: Add pin configuration to the device tree x86: Add an ICH6 pin configuration driver x86: gpio: Allow the pinctrl driver to set up the pin config x86: Drop all the old pin configuration code x86: Add support for running Intel reference code x86: dts: Update the pinctrl binding a little x86: Add basic support for broadwell x86: broadwell: Add a PCH driver x86: broadwell: Add a pinctrl driver x86: broadwell: Add a SATA driver x86: broadwell: Add a northbridge driver x86: broadwell: Add an LPC driver x86: broadwell: Add reference code support x86: broadwell: Add power-control support x86: broadwell: Add support for SDRAM setup x86: broadwell: Add a GPIO driver x86: broadwell: Add support for high-speed I/O lane with ME x86: Support a chained-boot development flow x86: broadwell: Add video support x86: Add a default address for reference code x86: Use white on black for the console on chromebooks x86: Update README for new developments x86: Add a function to set the IOAPIC ID x86: Fix a header nit in x86-chromebook.h x86: Add support for the samus chromebook
Makefile | 14 +- arch/arm/lib/Makefile | 3 +- arch/arm/lib/_uldivmod.S | 245 +++++++ arch/x86/Kconfig | 73 ++ arch/x86/cpu/Makefile | 2 + arch/x86/cpu/broadwell/Kconfig | 30 + arch/x86/cpu/broadwell/Makefile | 17 + arch/x86/cpu/broadwell/cpu.c | 761 ++++++++++++++++++++ arch/x86/cpu/broadwell/iobp.c | 144 ++++ arch/x86/cpu/broadwell/lpc.c | 77 ++ arch/x86/cpu/broadwell/me.c | 57 ++ arch/x86/cpu/broadwell/northbridge.c | 59 ++ arch/x86/cpu/broadwell/pch.c | 540 ++++++++++++++ arch/x86/cpu/broadwell/pinctrl_broadwell.c | 278 +++++++ arch/x86/cpu/broadwell/power_state.c | 89 +++ arch/x86/cpu/broadwell/refcode.c | 113 +++ arch/x86/cpu/broadwell/sata.c | 269 +++++++ arch/x86/cpu/broadwell/sdram.c | 307 ++++++++ arch/x86/cpu/cpu.c | 15 +- arch/x86/cpu/intel_common/Makefile | 16 + arch/x86/cpu/{ivybridge => intel_common}/car.S | 4 +- arch/x86/cpu/intel_common/cpu.c | 111 +++ arch/x86/cpu/intel_common/lpc.c | 100 +++ .../cpu/{ivybridge => intel_common}/me_status.c | 20 +- .../microcode_intel.c => intel_common/microcode.c} | 11 +- arch/x86/cpu/intel_common/mrc.c | 271 +++++++ arch/x86/cpu/intel_common/pch_common.c | 25 + .../{ivybridge => intel_common}/report_platform.c | 2 +- arch/x86/cpu/ioapic.c | 16 + arch/x86/cpu/ivybridge/Kconfig | 27 +- arch/x86/cpu/ivybridge/Makefile | 4 - arch/x86/cpu/ivybridge/bd82x6x.c | 17 +- arch/x86/cpu/ivybridge/cpu.c | 86 +-- arch/x86/cpu/ivybridge/early_me.c | 31 +- arch/x86/cpu/ivybridge/gma.c | 1 + arch/x86/cpu/ivybridge/lpc.c | 77 +- arch/x86/cpu/ivybridge/model_206ax.c | 3 +- arch/x86/cpu/ivybridge/northbridge.c | 5 +- arch/x86/cpu/ivybridge/sata.c | 47 +- arch/x86/cpu/ivybridge/sdram.c | 400 +++-------- arch/x86/cpu/mp_init.c | 11 +- arch/x86/cpu/start.S | 79 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 156 +++- arch/x86/dts/chromebook_samus.dts | 628 ++++++++++++++++ arch/x86/include/asm/arch-broadwell/cpu.h | 48 ++ arch/x86/include/asm/arch-broadwell/gpio.h | 91 +++ arch/x86/include/asm/arch-broadwell/iomap.h | 53 ++ arch/x86/include/asm/arch-broadwell/lpc.h | 32 + arch/x86/include/asm/arch-broadwell/me.h | 200 ++++++ arch/x86/include/asm/arch-broadwell/pch.h | 153 ++++ arch/x86/include/asm/arch-broadwell/pei_data.h | 177 +++++ arch/x86/include/asm/arch-broadwell/pm.h | 129 ++++ arch/x86/include/asm/arch-broadwell/rcb.h | 58 ++ arch/x86/include/asm/arch-broadwell/spi.h | 87 +++ arch/x86/include/asm/arch-ivybridge/me.h | 333 +-------- arch/x86/include/asm/arch-ivybridge/pch.h | 62 -- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 - arch/x86/include/asm/cpu.h | 27 + arch/x86/include/asm/cpu_common.h | 35 + arch/x86/include/asm/global_data.h | 24 + arch/x86/include/asm/gpio.h | 141 ---- arch/x86/include/asm/intel_regs.h | 28 + arch/x86/include/asm/io.h | 34 +- arch/x86/include/asm/ioapic.h | 2 + arch/x86/include/asm/lpc_common.h | 59 ++ arch/x86/include/asm/me_common.h | 372 ++++++++++ .../include/asm/{arch-ivybridge => }/microcode.h | 12 + arch/x86/include/asm/mrc_common.h | 55 ++ arch/x86/include/asm/pch_common.h | 56 ++ arch/x86/include/asm/processor.h | 2 +- arch/x86/include/asm/report_platform.h | 19 + arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/fsp_car.S | 2 + arch/x86/lib/pinctrl_ich6.c | 216 ++++++ board/coreboot/coreboot/coreboot.c | 5 - board/efi/efi-x86/efi.c | 5 - board/google/Kconfig | 13 + board/google/chromebook_link/link.c | 138 ---- board/google/chromebook_samus/Kconfig | 40 ++ board/google/chromebook_samus/MAINTAINERS | 6 + board/google/chromebook_samus/Makefile | 7 + board/google/chromebook_samus/samus.c | 18 + board/google/chromebox_panther/panther.c | 4 - board/intel/bayleybay/bayleybay.c | 5 - board/intel/cougarcanyon2/cougarcanyon2.c | 6 +- board/intel/crownbay/crownbay.c | 5 - board/intel/galileo/galileo.c | 5 - board/intel/minnowmax/minnowmax.c | 8 - common/board_f.c | 7 + common/board_r.c | 4 +- configs/bayleybay_defconfig | 2 + configs/chromebook_samus_defconfig | 51 ++ configs/cougarcanyon2_defconfig | 2 + configs/crownbay_defconfig | 2 + configs/galileo_defconfig | 2 + configs/minnowmax_defconfig | 6 +- doc/README.x86 | 97 ++- .../gpio/intel,x86-broadwell-pinctrl.txt | 208 ++++++ .../gpio/intel,x86-pinctrl.txt | 22 +- drivers/core/syscon-uclass.c | 1 + drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/intel_broadwell_gpio.c | 198 +++++ drivers/gpio/intel_ich6_gpio.c | 191 +---- drivers/input/i8042.c | 4 + drivers/serial/serial-uclass.c | 2 +- drivers/video/Kconfig | 14 +- drivers/video/Makefile | 2 + drivers/video/broadwell_igd.c | 797 +++++++++++++++++++++ drivers/video/i915_reg.h | 362 ++++++++++ include/configs/chromebook_samus.h | 29 + include/configs/x86-chromebook.h | 8 +- include/dt-bindings/gpio/x86-gpio.h | 12 + include/fdtdec.h | 2 - include/i8042.h | 1 + lib/dhry/cmd_dhry.c | 8 +- lib/fdtdec.c | 2 - 118 files changed, 8550 insertions(+), 1518 deletions(-) create mode 100644 arch/arm/lib/_uldivmod.S create mode 100644 arch/x86/cpu/broadwell/Kconfig create mode 100644 arch/x86/cpu/broadwell/Makefile create mode 100644 arch/x86/cpu/broadwell/cpu.c create mode 100644 arch/x86/cpu/broadwell/iobp.c create mode 100644 arch/x86/cpu/broadwell/lpc.c create mode 100644 arch/x86/cpu/broadwell/me.c create mode 100644 arch/x86/cpu/broadwell/northbridge.c create mode 100644 arch/x86/cpu/broadwell/pch.c create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c create mode 100644 arch/x86/cpu/broadwell/power_state.c create mode 100644 arch/x86/cpu/broadwell/refcode.c create mode 100644 arch/x86/cpu/broadwell/sata.c create mode 100644 arch/x86/cpu/broadwell/sdram.c create mode 100644 arch/x86/cpu/intel_common/Makefile rename arch/x86/cpu/{ivybridge => intel_common}/car.S (98%) create mode 100644 arch/x86/cpu/intel_common/cpu.c create mode 100644 arch/x86/cpu/intel_common/lpc.c rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%) rename arch/x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} (96%) create mode 100644 arch/x86/cpu/intel_common/mrc.c create mode 100644 arch/x86/cpu/intel_common/pch_common.c rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%) create mode 100644 arch/x86/dts/chromebook_samus.dts create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h create mode 100644 arch/x86/include/asm/arch-broadwell/me.h create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h create mode 100644 arch/x86/include/asm/cpu_common.h create mode 100644 arch/x86/include/asm/intel_regs.h create mode 100644 arch/x86/include/asm/lpc_common.h create mode 100644 arch/x86/include/asm/me_common.h rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (63%) create mode 100644 arch/x86/include/asm/mrc_common.h create mode 100644 arch/x86/include/asm/pch_common.h create mode 100644 arch/x86/include/asm/report_platform.h create mode 100644 arch/x86/lib/pinctrl_ich6.c create mode 100644 board/google/chromebook_samus/Kconfig create mode 100644 board/google/chromebook_samus/MAINTAINERS create mode 100644 board/google/chromebook_samus/Makefile create mode 100644 board/google/chromebook_samus/samus.c create mode 100644 configs/chromebook_samus_defconfig create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt create mode 100644 drivers/gpio/intel_broadwell_gpio.c create mode 100644 drivers/video/broadwell_igd.c create mode 100644 drivers/video/i915_reg.h create mode 100644 include/configs/chromebook_samus.h