cs0_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.
So, update cs0_row macro to make use of both sys_reg2, sys_reg3.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++-- drivers/ram/rockchip/sdram_rk3399.c | 4 +++- 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 7e0b491859..3d1d5badb4 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -51,8 +51,6 @@ SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ @@ -64,6 +62,12 @@ #define SYS_REG_DBW_MASK 3 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 4463fc84c8..2408246d0d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1006,6 +1006,7 @@ static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *sdram_params) { u32 sys_reg2 = 0; + u32 sys_reg3 = 0; unsigned int channel, idx;
sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); @@ -1026,10 +1027,10 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel); - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch; noc_timing = &sdram_params->ch[channel].noc_timings; @@ -1051,6 +1052,7 @@ static void dram_all_config(struct dram_info *dram, }
writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, sdram_params->base.stride << 10);