This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- board/google/chromebook_link/Kconfig | 3 +-- 4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..bda7a0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+config PCIE_ECAM_BASE + hex + default 0xe0000000 + help + This is the memory-mapped address of PCI configuration space, which + is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. It can be set up almost + anywhere. Before it is set up, it is possible to access PCI + configuration space through I/O access, but memory access is more + convenient. Using this, PCI can be scanned and configured. This + should be set to a region that does not conflict with memory + assigned to PCI devices - i.e. the memory and prefetch regions, as + passed to pci_set_region(). + endmenu diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4963448..766b385 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -757,7 +757,7 @@ int dram_init(void) .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_PCIE_ECAM_BASE, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index cf7457f..c960525 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,7 +43,7 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
/* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f3..ea45472 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192
-config MMCONF_BASE_ADDRESS - hex +config PCIE_ECAM_BASE default 0xf0000000
config EARLY_POST_CROS_EC