
6 Jun
2017
6 Jun
'17
11:08 p.m.
On 2 June 2017 at 03:19, Romain Perier romain.perier@collabora.com wrote:
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit 0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and introduces random delays and data lose.
This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE with the right shift.
Signed-off-by: Romain Perier romain.perier@collabora.com
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org