From: Stephen Warren swarren@nvidia.com
U-Boot is compiled for a single board, which in turn uses a specific SoC. There's no need to make runtime decisions based on CPU count. While there's certainly an argument for making the code support different SoCs at run-time, the Tegra code is so far from that possible ideal that the existing runtime code is an anomaly. If this changes in the future, all runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/cpu.c | 31 +++---------------------------- 1 file changed, 3 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index cc60908677a1..30964dde8b19 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> @@ -15,29 +14,6 @@ #include "pmc.h" #include "scu.h"
-int get_num_cpus(void) -{ - struct apb_misc_gp_ctlr *gp; - uint rev; - debug("%s entry\n", __func__); - - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - - switch (rev) { - case CHIPID_TEGRA20: - return 2; - break; - case CHIPID_TEGRA30: - case CHIPID_TEGRA114: - case CHIPID_TEGRA124: - case CHIPID_TEGRA210: - default: - return 4; - break; - } -} - /* * Timing tables for each SOC for all four oscillator options. */ @@ -283,7 +259,7 @@ void enable_cpu_clock(int enable) */ clk = readl(&clkrst->crc_clk_cpu_cmplx); clk |= 1 << CPU1_CLK_STP_SHIFT; - if (get_num_cpus() == 4) + if (MAX_NUM_CPU == 4) clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
/* Stop/Unstop the CPU clock */ @@ -358,12 +334,11 @@ void reset_A9_cpu(int reset) * are multiple processors in the CPU complex. */ int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug; - int num_cpus = get_num_cpus(); int cpu;
debug("%s entry\n", __func__); /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ - for (cpu = 1; cpu < num_cpus; cpu++) + for (cpu = 1; cpu < MAX_NUM_CPU; cpu++) reset_cmplx_set_enable(cpu, mask, 1); reset_cmplx_set_enable(0, mask, reset);
@@ -393,7 +368,7 @@ void clock_enable_coresight(int enable) rst = CORESIGHT_UNLOCK; writel(rst, CSITE_CPU_DBG0_LAR); writel(rst, CSITE_CPU_DBG1_LAR); - if (get_num_cpus() == 4) { + if (MAX_NUM_CPU == 4) { writel(rst, CSITE_CPU_DBG2_LAR); writel(rst, CSITE_CPU_DBG3_LAR); }