Extract from Linux mainline patch: The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs).
Acked-by: Duc Dang dhdang@apm.com Acked-by: Carlo Caione carlo@endlessm.com Acked-by: Michal Simek michal.simek@xilinx.com Acked-by: Krzysztof Kozlowski k.kozlowski@samsung.com Acked-by: Dinh Nguyen dinguyen@opensource.altera.com Acked-by: Masahiro Yamada yamada.masahiro@socionext.com Signed-off-by: Marc Zyngier marc.zyngier@arm.com Signed-off-by: Arnd Bergmann arnd@arndb.de Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 70d28a3679f5..3dd17e6c3f1e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -272,10 +272,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; };
edac {