30 Mar
2019
30 Mar
'19
10:18 p.m.
On Wed, 27 Mar 2019 at 17:50, Trent Piepho tpiepho@impinj.com wrote:
The cache flush of the kernel load area needs to be aligned outward to the DMA cache alignment. The operations are simpler if we think of this as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find the length of the flushed region by subtracting the former from the latter.
Cc: Tom Rini trini@konsulko.com Cc: Simon Glass sjg@chromium.org Cc: Bryan O'Donoghue bryan.odonoghue@linaro.org Signed-off-by: Trent Piepho tpiepho@impinj.com
common/bootm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org