For ease of use and accounting a condition that on SH4 pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to unimplemented __iomem() conversion, this change fixes access to SDRAM memory by PCI devices.
This change also generalizes PCI system memory configuration, which is taken from board specific defines rather than hardcoded in the PCI host driver.
Signed-off-by: Vladimir Zapolskiy vz@mleia.com --- drivers/pci/pci_sh7751.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index 420ae81..8a50445 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -66,9 +66,6 @@ #define SH7751_PCI_IO_BASE 0xFE240000 #define SH7751_PCI_IO_SIZE 0x00040000
-#define SH7751_CS3_BASE_ADDR 0x0C000000 -#define SH7751_P2CS3_BASE_ADDR 0xAC000000 - #define SH7751_PCIPAR (vu_long *)0xFE2001C0 #define SH7751_PCIPDR (vu_long *)0xFE200220
@@ -153,11 +150,12 @@ int pci_sh7751_init(struct pci_controller *hose)
/* Set up target memory mappings (for external DMA access) */ /* Map both P0 and P2 range to Area 3 RAM for ease of use */ - p4_out((64 - 1) << 20, SH7751_PCILSR0); - p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0); + p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); + p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); + p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); + p4_out(0, SH7751_PCILSR1); p4_out(0, SH7751_PCILAR1); - p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5); p4_out(0xd0000000, SH7751_PCICONF6);
/* Map memory window to same address on PCI bus */