Vince Asbridge wrote:
We have an 8548 design, which implements a DDR2 on a SODIMM We have an issue with dual rank memory (specific part number Viking VR5DR287218EBSS1), which is a 1G ECC Registered SODIMM part, with two ranks. Our platform wires CS0 and CS1 to the SODIMM slot. At uBoot, all is well. Memory is discovered as ECC 533, 1G DDR2 64Bit 4 beat bursts, and mtest can read and write all 1G of the SODIMM.
[...]
Other DDR2s (identical except for vendor and # of ranks), work perfectly! Anyone got a clue what I could look at to try to figure this out? We've tried enable / disable ECC at uboot We've tried enable / disable Interleaving at uboot uboot always works (and can read/write entire DDR), Linux always hangs on boot!
U-Boot is too gentle when testing SDRAM. Make sure the caches are enabled under U-Boot, and put on heavy stress with DMA, pipelined prefetch's, etc. This is what your CPU is enduring under Linux.
Your question is definitely a question for the U-Boot mailing list. BTW, what is the version of U-Boot in use? U-Boot is still missing the following patch:
MPC85xx BA bits not set for 3-bit bank address DIMM of CS1
The current implementation set the number of bank address bits (BA) in the processor for CS0 but not for CS1.
Signed-off-by: Stephane Fillod stephane.fillod@thomson.net
--- u-boot/cpu/mpc85xx/spd_sdram.c +++ u-boot/cpu/mpc85xx/spd_sdram.c @@ -365,6 +365,7 @@ ddr->cs1_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
Otherwise, recompile with -DDEBUG and CFG_CMD_SDRAM, grab the Viking datasheet and a scope, and a full cup of coffee/tea much needed during cross-checking :-)
Cheers